2 * MPC8260 Internal Memory Map
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 * The Internal Memory Map of the 8260. I don't know how generic
6 * this will be, as I don't have any knowledge of the subsequent
7 * parts at this time. I copied this from the 8xx_immap.h.
10 #define __IMMAP_82XX__
12 /* System configuration registers.
14 typedef struct sys_conf {
42 /* Memory controller registers.
44 typedef struct mem_ctlr {
99 /* System Integration Timers.
101 typedef struct sys_int_timers {
119 typedef struct pci_config {
248 #define PISCR_PIRQ_MASK ((ushort)0xff00)
249 #define PISCR_PS ((ushort)0x0080)
250 #define PISCR_PIE ((ushort)0x0004)
251 #define PISCR_PTF ((ushort)0x0002)
252 #define PISCR_PTE ((ushort)0x0001)
254 /* Interrupt Controller.
256 typedef struct interrupt_controller {
273 typedef struct clk_and_reset {
283 /* Input/Output Port control/status registers.
284 * Names consistent with processor manual, although they are different
285 * from the original 8xx names.......
287 typedef struct io_port {
314 /* Communication Processor Module Timers
316 typedef struct cpm_timers {
344 /* DMA control/status registers.
346 typedef struct sdma_csr {
385 u_char fcc_ftirr_phy[4];
405 typedef struct scc { /* Serial communication channels */
420 typedef struct smc { /* Serial management channels */
430 /* Serial Peripheral Interface.
432 typedef struct im_spi {
445 typedef struct cpmux {
460 typedef struct siram {
483 typedef struct comm_proc {
496 /* ...and the whole thing wrapped up....
498 typedef struct immap {
499 /* Some references are into the unique and known dpram spaces,
500 * others are from the generic base.
502 #define im_dprambase im_dpram1
503 u_char im_dpram1[16*1024];
505 u_char im_dpram2[4*1024];
507 u_char im_dpram3[4*1024];
510 sysconf8260_t im_siu_conf; /* SIU Configuration */
511 memctl8260_t im_memctl; /* Memory Controller */
512 sit8260_t im_sit; /* System Integration Timers */
513 pci8260_t im_pci; /* PCI Configuration */
514 intctl8260_t im_intctl; /* Interrupt Controller */
515 car8260_t im_clkrst; /* Clocks and reset */
516 iop8260_t im_ioport; /* IO Port control/status */
517 cpmtimer8260_t im_cpmtimer; /* CPM timers */
518 sdma8260_t im_sdma; /* SDMA control/status */
520 fcc_t im_fcc[3]; /* Three FCCs */
524 /* First set of baud rate generators.
534 i2c8260_t im_i2c; /* I2C control/status */
535 cpm8260_t im_cpm; /* Communication processor */
537 /* Second set of baud rate generators.
544 scc_t im_scc[4]; /* Four SCCs */
545 smc_t im_smc[2]; /* Couple of SMCs */
546 im_spi_t im_spi; /* A SPI */
547 cpmux_t im_cpmux; /* CPM clock route mux */
548 siramctl_t im_siramctl1; /* First SI RAM Control */
549 mcc_t im_mcc1; /* First MCC */
550 siramctl_t im_siramctl2; /* Second SI RAM Control */
551 mcc_t im_mcc2; /* Second MCC */
555 ushort im_si1txram[256];
557 ushort im_si1rxram[256];
559 ushort im_si2txram[256];
561 ushort im_si2rxram[256];
566 #endif /* __IMMAP_82XX__ */