2 * MPC8260 Internal Memory Map
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 * The Internal Memory Map of the 8260. I don't know how generic
6 * this will be, as I don't have any knowledge of the subsequent
7 * parts at this time. I copied this from the 8xx_immap.h.
10 #define __IMMAP_82XX__
12 /* System configuration registers.
14 typedef struct sys_conf {
42 /* Memory controller registers.
44 typedef struct mem_ctlr {
99 /* System Integration Timers.
101 typedef struct sys_int_timers {
119 typedef struct pci_config {
244 #define PISCR_PIRQ_MASK ((ushort)0xff00)
245 #define PISCR_PS ((ushort)0x0080)
246 #define PISCR_PIE ((ushort)0x0004)
247 #define PISCR_PTF ((ushort)0x0002)
248 #define PISCR_PTE ((ushort)0x0001)
250 /* Interrupt Controller.
252 typedef struct interrupt_controller {
269 typedef struct clk_and_reset {
279 /* Input/Output Port control/status registers.
280 * Names consistent with processor manual, although they are different
281 * from the original 8xx names.......
283 typedef struct io_port {
310 /* Communication Processor Module Timers
312 typedef struct cpm_timers {
340 /* DMA control/status registers.
342 typedef struct sdma_csr {
381 u_char fcc_ftirr_phy[4];
401 typedef struct scc { /* Serial communication channels */
416 typedef struct smc { /* Serial management channels */
426 /* Serial Peripheral Interface.
428 typedef struct im_spi {
441 typedef struct cpmux {
456 typedef struct siram {
479 typedef struct comm_proc {
492 /* ...and the whole thing wrapped up....
494 typedef struct immap {
495 /* Some references are into the unique and known dpram spaces,
496 * others are from the generic base.
498 #define im_dprambase im_dpram1
499 u_char im_dpram1[16*1024];
501 u_char im_dpram2[4*1024];
503 u_char im_dpram3[4*1024];
506 sysconf8260_t im_siu_conf; /* SIU Configuration */
507 memctl8260_t im_memctl; /* Memory Controller */
508 sit8260_t im_sit; /* System Integration Timers */
509 pci8260_t im_pci; /* PCI Configuration */
510 intctl8260_t im_intctl; /* Interrupt Controller */
511 car8260_t im_clkrst; /* Clocks and reset */
512 iop8260_t im_ioport; /* IO Port control/status */
513 cpmtimer8260_t im_cpmtimer; /* CPM timers */
514 sdma8260_t im_sdma; /* SDMA control/status */
516 fcc_t im_fcc[3]; /* Three FCCs */
520 /* First set of baud rate generators.
530 i2c8260_t im_i2c; /* I2C control/status */
531 cpm8260_t im_cpm; /* Communication processor */
533 /* Second set of baud rate generators.
540 scc_t im_scc[4]; /* Four SCCs */
541 smc_t im_smc[2]; /* Couple of SMCs */
542 im_spi_t im_spi; /* A SPI */
543 cpmux_t im_cpmux; /* CPM clock route mux */
544 siramctl_t im_siramctl1; /* First SI RAM Control */
545 mcc_t im_mcc1; /* First MCC */
546 siramctl_t im_siramctl2; /* Second SI RAM Control */
547 mcc_t im_mcc2; /* Second MCC */
551 ushort im_si1txram[256];
553 ushort im_si1rxram[256];
555 ushort im_si2txram[256];
557 ushort im_si2rxram[256];
562 #endif /* __IMMAP_82XX__ */