2 * PowerPC memory management structures
8 #include <linux/config.h>
11 /* Hardware Page Table Entry */
13 #ifdef CONFIG_PPC64BRIDGE
14 unsigned long long vsid:52;
19 unsigned long long rpn:52;
20 #else /* CONFIG_PPC64BRIDGE */
21 unsigned long v:1; /* Entry is valid */
22 unsigned long vsid:24; /* Virtual segment identifier */
23 unsigned long h:1; /* Hash algorithm indicator */
24 unsigned long api:6; /* Abbreviated page index */
25 unsigned long rpn:20; /* Real (physical) page number */
26 #endif /* CONFIG_PPC64BRIDGE */
27 unsigned long :3; /* Unused */
28 unsigned long r:1; /* Referenced */
29 unsigned long c:1; /* Changed */
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */
32 unsigned long m:1; /* Memory coherence */
33 unsigned long g:1; /* Guarded */
34 unsigned long :1; /* Unused */
35 unsigned long pp:2; /* Page protection */
38 /* Values for PP (assumes Ks=0, Kp=1) */
39 #define PP_RWXX 0 /* Supervisor read/write, User none */
40 #define PP_RWRX 1 /* Supervisor read/write, User read */
41 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
42 #define PP_RXRX 3 /* Supervisor read, User read */
44 /* Segment Register */
45 typedef struct _SEGREG {
46 unsigned long t:1; /* Normal or I/O type */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
48 unsigned long kp:1; /* User 'key' (normally 1) */
49 unsigned long n:1; /* No-execute */
50 unsigned long :4; /* Unused */
51 unsigned long vsid:24; /* Virtual Segment Identifier */
54 /* Block Address Translation (BAT) Registers */
55 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
56 unsigned long bepi:15; /* Effective page index (virtual address) */
57 unsigned long :8; /* unused */
59 unsigned long i:1; /* Cache inhibit */
60 unsigned long m:1; /* Memory coherence */
61 unsigned long ks:1; /* Supervisor key (normally 0) */
62 unsigned long kp:1; /* User key (normally 1) */
63 unsigned long pp:2; /* Page access protections */
66 typedef struct _BATU { /* Upper part of BAT (all except 601) */
67 #ifdef CONFIG_PPC64BRIDGE
68 unsigned long long bepi:47;
69 #else /* CONFIG_PPC64BRIDGE */
70 unsigned long bepi:15; /* Effective page index (virtual address) */
71 #endif /* CONFIG_PPC64BRIDGE */
72 unsigned long :4; /* Unused */
73 unsigned long bl:11; /* Block size mask */
74 unsigned long vs:1; /* Supervisor valid */
75 unsigned long vp:1; /* User valid */
78 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
79 unsigned long brpn:15; /* Real page index (physical address) */
80 unsigned long :10; /* Unused */
81 unsigned long v:1; /* Valid bit */
82 unsigned long bl:6; /* Block size mask */
85 typedef struct _BATL { /* Lower part of BAT (all except 601) */
86 #ifdef CONFIG_PPC64BRIDGE
87 unsigned long long brpn:47;
88 #else /* CONFIG_PPC64BRIDGE */
89 unsigned long brpn:15; /* Real page index (physical address) */
90 #endif /* CONFIG_PPC64BRIDGE */
91 unsigned long :10; /* Unused */
92 unsigned long w:1; /* Write-thru cache */
93 unsigned long i:1; /* Cache inhibit */
94 unsigned long m:1; /* Memory coherence */
95 unsigned long g:1; /* Guarded (MBZ in IBAT) */
96 unsigned long :1; /* Unused */
97 unsigned long pp:2; /* Page access protections */
100 typedef struct _BAT {
101 BATU batu; /* Upper register */
102 BATL batl; /* Lower register */
105 typedef struct _P601_BAT {
106 P601_BATU batu; /* Upper register */
107 P601_BATL batl; /* Lower register */
111 * Simulated two-level MMU. This structure is used by the kernel
112 * to keep track of MMU mappings and is used to update/maintain
113 * the hardware HASH table which is really a cache of mappings.
115 * The simulated structures mimic the hardware available on other
116 * platforms, notably the 80x86 and 680x0.
119 typedef struct _pte {
120 unsigned long page_num:20;
121 unsigned long flags:12; /* Page flags (some unused bits) */
124 #define PD_SHIFT (10+12) /* Page directory */
125 #define PD_MASK 0x02FF
126 #define PT_SHIFT (12) /* Page Table */
127 #define PT_MASK 0x02FF
128 #define PG_SHIFT (12) /* Page Entry */
133 typedef struct _MMU_context {
134 SEGREG segs[16]; /* Segment registers */
135 pte **pmap; /* Two-level page-map structure */
138 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
139 extern void _tlbia(void); /* invalidate all TLB entries */
142 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
143 DBAT0, DBAT1, DBAT2, DBAT3,
144 #ifdef CONFIG_HIGH_BATS
145 IBAT4, IBAT5, IBAT6, IBAT7,
146 DBAT4, DBAT5, DBAT6, DBAT7
150 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
151 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
153 #endif /* __ASSEMBLY__ */
155 /* Block size masks */
156 #define BL_128K 0x000
157 #define BL_256K 0x001
158 #define BL_512K 0x003
166 #define BL_128M 0x3FF
167 #define BL_256M 0x7FF
169 /* BAT Access Protection */
170 #define BPP_XX 0x00 /* No access */
171 #define BPP_RX 0x01 /* Read only */
172 #define BPP_RW 0x02 /* Read/write */
174 /* Used to set up SDR1 register */
175 #define HASH_TABLE_SIZE_64K 0x00010000
176 #define HASH_TABLE_SIZE_128K 0x00020000
177 #define HASH_TABLE_SIZE_256K 0x00040000
178 #define HASH_TABLE_SIZE_512K 0x00080000
179 #define HASH_TABLE_SIZE_1M 0x00100000
180 #define HASH_TABLE_SIZE_2M 0x00200000
181 #define HASH_TABLE_SIZE_4M 0x00400000
182 #define HASH_TABLE_MASK_64K 0x000
183 #define HASH_TABLE_MASK_128K 0x001
184 #define HASH_TABLE_MASK_256K 0x003
185 #define HASH_TABLE_MASK_512K 0x007
186 #define HASH_TABLE_MASK_1M 0x00F
187 #define HASH_TABLE_MASK_2M 0x01F
188 #define HASH_TABLE_MASK_4M 0x03F
190 /* Control/status registers for the MPC8xx.
191 * A write operation to these registers causes serialized access.
192 * During software tablewalk, the registers used perform mask/shift-add
193 * operations when written/read. A TLB entry is created when the Mx_RPN
194 * is written, and the contents of several registers are used to
197 #define MI_CTR 784 /* Instruction TLB control register */
198 #define MI_GPM 0x80000000 /* Set domain manager mode */
199 #define MI_PPM 0x40000000 /* Set subpage protection */
200 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
201 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
202 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
203 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
204 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
206 /* These are the Ks and Kp from the PowerPC books. For proper operation,
210 #define MI_Ks 0x80000000 /* Should not be set */
211 #define MI_Kp 0x40000000 /* Should always be set */
213 /* The effective page number register. When read, contains the information
214 * about the last instruction TLB miss. When MI_RPN is written, bits in
215 * this register are used to create the TLB entry.
218 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
219 #define MI_EVALID 0x00000200 /* Entry is valid */
220 #define MI_ASIDMASK 0x0000000f /* ASID match value */
221 /* Reset value is undefined */
223 /* A "level 1" or "segment" or whatever you want to call it register.
224 * For the instruction TLB, it contains bits that get loaded into the
225 * TLB entry when the MI_RPN is written.
228 #define MI_APG 0x000001e0 /* Access protection group (0) */
229 #define MI_GUARDED 0x00000010 /* Guarded storage */
230 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
231 #define MI_PS8MEG 0x0000000c /* 8M page size */
232 #define MI_PS512K 0x00000004 /* 512K page size */
233 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
234 #define MI_SVALID 0x00000001 /* Segment entry is valid */
235 /* Reset value is undefined */
237 /* Real page number. Defined by the pte. Writing this register
238 * causes a TLB entry to be created for the instruction TLB, using
239 * additional information from the MI_EPN, and MI_TWC registers.
243 /* Define an RPN value for mapping kernel memory to large virtual
244 * pages for boot initialization. This has real page number of 0,
245 * large page size, shared page, cache enabled, and valid.
246 * Also mark all subpages valid and write access.
248 #define MI_BOOTINIT 0x000001fd
250 #define MD_CTR 792 /* Data TLB control register */
251 #define MD_GPM 0x80000000 /* Set domain manager mode */
252 #define MD_PPM 0x40000000 /* Set subpage protection */
253 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
254 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
255 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
256 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
257 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
258 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
259 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
261 #define M_CASID 793 /* Address space ID (context) to match */
262 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
265 /* These are the Ks and Kp from the PowerPC books. For proper operation,
269 #define MD_Ks 0x80000000 /* Should not be set */
270 #define MD_Kp 0x40000000 /* Should always be set */
272 /* The effective page number register. When read, contains the information
273 * about the last instruction TLB miss. When MD_RPN is written, bits in
274 * this register are used to create the TLB entry.
277 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
278 #define MD_EVALID 0x00000200 /* Entry is valid */
279 #define MD_ASIDMASK 0x0000000f /* ASID match value */
280 /* Reset value is undefined */
282 /* The pointer to the base address of the first level page table.
283 * During a software tablewalk, reading this register provides the address
284 * of the entry associated with MD_EPN.
287 #define M_L1TB 0xfffff000 /* Level 1 table base address */
288 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
289 /* Reset value is undefined */
291 /* A "level 1" or "segment" or whatever you want to call it register.
292 * For the data TLB, it contains bits that get loaded into the TLB entry
293 * when the MD_RPN is written. It is also provides the hardware assist
294 * for finding the PTE address during software tablewalk.
297 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
298 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
299 #define MD_APG 0x000001e0 /* Access protection group (0) */
300 #define MD_GUARDED 0x00000010 /* Guarded storage */
301 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
302 #define MD_PS8MEG 0x0000000c /* 8M page size */
303 #define MD_PS512K 0x00000004 /* 512K page size */
304 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
305 #define MD_WT 0x00000002 /* Use writethrough page attribute */
306 #define MD_SVALID 0x00000001 /* Segment entry is valid */
307 /* Reset value is undefined */
310 /* Real page number. Defined by the pte. Writing this register
311 * causes a TLB entry to be created for the data TLB, using
312 * additional information from the MD_EPN, and MD_TWC registers.
316 /* This is a temporary storage register that could be used to save
317 * a processor working register during a tablewalk.
322 * At present, all PowerPC 400-class processors share a similar TLB
323 * architecture. The instruction and data sides share a unified,
324 * 64-entry, fully-associative TLB which is maintained totally under
325 * software control. In addition, the instruction side has a
326 * hardware-managed, 4-entry, fully- associative TLB which serves as a
327 * first level to the shared TLB. These two TLBs are known as the UTLB
328 * and ITLB, respectively.
331 #define PPC4XX_TLB_SIZE 64
334 * TLB entries are defined by a "high" tag portion and a "low" data
335 * portion. On all architectures, the data portion is 32-bits.
337 * TLB entries are managed entirely under software control by reading,
338 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
346 #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
347 #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
348 #define MAS0_NV(x) ((x) & 0x00000FFF)
350 #define MAS1_VALID 0x80000000
351 #define MAS1_IPROT 0x40000000
352 #define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
353 #define MAS1_TS 0x00001000
354 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
356 #define MAS2_EPN 0xFFFFF000
357 #define MAS2_X0 0x00000040
358 #define MAS2_X1 0x00000020
359 #define MAS2_W 0x00000010
360 #define MAS2_I 0x00000008
361 #define MAS2_M 0x00000004
362 #define MAS2_G 0x00000002
363 #define MAS2_E 0x00000001
365 #define MAS3_RPN 0xFFFFF000
366 #define MAS3_U0 0x00000200
367 #define MAS3_U1 0x00000100
368 #define MAS3_U2 0x00000080
369 #define MAS3_U3 0x00000040
370 #define MAS3_UX 0x00000020
371 #define MAS3_SX 0x00000010
372 #define MAS3_UW 0x00000008
373 #define MAS3_SW 0x00000004
374 #define MAS3_UR 0x00000002
375 #define MAS3_SR 0x00000001
377 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
378 #define MAS4_TIDDSEL 0x000F0000
379 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
380 #define MAS4_X0D 0x00000040
381 #define MAS4_X1D 0x00000020
382 #define MAS4_WD 0x00000010
383 #define MAS4_ID 0x00000008
384 #define MAS4_MD 0x00000004
385 #define MAS4_GD 0x00000002
386 #define MAS4_ED 0x00000001
388 #define MAS6_SPID0 0x3FFF0000
389 #define MAS6_SPID1 0x00007FFE
390 #define MAS6_SAS 0x00000001
391 #define MAS6_SPID MAS6_SPID0
393 #define MAS7_RPN 0xFFFFFFFF
395 #define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
396 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
397 #define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
398 ((((v) << 31) & MAS1_VALID) |\
399 (((iprot) << 30) & MAS1_IPROT) |\
401 (((ts) << 12) & MAS1_TS) |\
403 #define FSL_BOOKE_MAS2(epn, wimge) \
404 (((epn) & MAS3_RPN) | (wimge))
405 #define FSL_BOOKE_MAS3(rpn, user, perms) \
406 (((rpn) & MAS3_RPN) | (user) | (perms))
408 #define BOOKE_PAGESZ_1K 0
409 #define BOOKE_PAGESZ_4K 1
410 #define BOOKE_PAGESZ_16K 2
411 #define BOOKE_PAGESZ_64K 3
412 #define BOOKE_PAGESZ_256K 4
413 #define BOOKE_PAGESZ_1M 5
414 #define BOOKE_PAGESZ_4M 6
415 #define BOOKE_PAGESZ_16M 7
416 #define BOOKE_PAGESZ_64M 8
417 #define BOOKE_PAGESZ_256M 9
418 #define BOOKE_PAGESZ_1G 10
419 #define BOOKE_PAGESZ_4G 11
420 #define BOOKE_PAGESZ_16GB 12
421 #define BOOKE_PAGESZ_64GB 13
422 #define BOOKE_PAGESZ_256GB 14
423 #define BOOKE_PAGESZ_1TB 15
427 extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
429 u8 ts, u8 esel, u8 tsize, u8 iprot);
430 extern void disable_tlb(u8 esel);
431 extern void invalidate_tlb(u8 tlb);
432 extern void init_tlbs(void);
434 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
435 { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
436 .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
438 struct fsl_e_tlb_entry {
450 extern struct fsl_e_tlb_entry tlb_table[];
451 extern int num_tlb_entries;
455 #if defined(CONFIG_MPC86xx)
456 #define LAWBAR_BASE_ADDR 0x00FFFFFF
457 #define LAWAR_TRGT_IF 0x01F00000
459 #define LAWBAR_BASE_ADDR 0x000FFFFF
460 #define LAWAR_TRGT_IF 0x00F00000
462 #define LAWAR_EN 0x80000000
463 #define LAWAR_SIZE 0x0000003F
465 #define LAWAR_TRGT_IF_PCI 0x00000000
466 #define LAWAR_TRGT_IF_PCI1 0x00000000
467 #define LAWAR_TRGT_IF_PCIX 0x00000000
468 #define LAWAR_TRGT_IF_PCI2 0x00100000
469 #define LAWAR_TRGT_IF_PCIE1 0x00200000
470 #define LAWAR_TRGT_IF_PCIE2 0x00100000
471 #define LAWAR_TRGT_IF_PCIE3 0x00300000
472 #define LAWAR_TRGT_IF_LBC 0x00400000
473 #define LAWAR_TRGT_IF_CCSR 0x00800000
474 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
475 #define LAWAR_TRGT_IF_RIO 0x00c00000
476 #define LAWAR_TRGT_IF_DDR 0x00f00000
477 #define LAWAR_TRGT_IF_DDR1 0x00f00000
478 #define LAWAR_TRGT_IF_DDR2 0x01600000
480 #define LAWAR_SIZE_BASE 0xa
481 #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
482 #define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
483 #define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
484 #define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
485 #define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
486 #define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
487 #define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
488 #define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
489 #define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
490 #define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
491 #define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
492 #define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
493 #define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
494 #define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
495 #define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
496 #define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
497 #define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
498 #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
499 #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
500 #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
501 #define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
502 #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
503 #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
504 #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
508 #define TLB_VALID 0x00000200
510 /* Supported page sizes */
512 #define SZ_1K 0x00000000
513 #define SZ_4K 0x00000010
514 #define SZ_16K 0x00000020
515 #define SZ_64K 0x00000030
516 #define SZ_256K 0x00000040
517 #define SZ_1M 0x00000050
518 #define SZ_16M 0x00000070
519 #define SZ_256M 0x00000090
521 /* Storage attributes */
522 #define SA_W 0x00000800 /* Write-through */
523 #define SA_I 0x00000400 /* Caching inhibited */
524 #define SA_M 0x00000200 /* Memory coherence */
525 #define SA_G 0x00000100 /* Guarded */
526 #define SA_E 0x00000080 /* Endian */
529 #define AC_X 0x00000024 /* Execute */
530 #define AC_W 0x00000012 /* Write */
531 #define AC_R 0x00000009 /* Read */
533 /* Some handy macros */
535 #define EPN(e) ((e) & 0xfffffc00)
536 #define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
537 #define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
538 #define TLB2(a) ((a) & 0x00000fbf)
540 #define tlbtab_start\
550 #define tlbentry(epn,sz,rpn,erpn,attr)\
551 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
553 /*----------------------------------------------------------------------------+
554 | TLB specific defines.
555 +----------------------------------------------------------------------------*/
556 #define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
557 #define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
558 #define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
559 #define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
560 #define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
561 #define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
562 #define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
563 #define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
564 #define TLB_256MB_SIZE 0x10000000
565 #define TLB_16MB_SIZE 0x01000000
566 #define TLB_1MB_SIZE 0x00100000
567 #define TLB_256KB_SIZE 0x00040000
568 #define TLB_64KB_SIZE 0x00010000
569 #define TLB_16KB_SIZE 0x00004000
570 #define TLB_4KB_SIZE 0x00001000
571 #define TLB_1KB_SIZE 0x00000400
573 #define TLB_WORD0_EPN_MASK 0xFFFFFC00
574 #define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
575 #define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
576 #define TLB_WORD0_V_MASK 0x00000200
577 #define TLB_WORD0_V_ENABLE 0x00000200
578 #define TLB_WORD0_V_DISABLE 0x00000000
579 #define TLB_WORD0_TS_MASK 0x00000100
580 #define TLB_WORD0_TS_1 0x00000100
581 #define TLB_WORD0_TS_0 0x00000000
582 #define TLB_WORD0_SIZE_MASK 0x000000F0
583 #define TLB_WORD0_SIZE_1KB 0x00000000
584 #define TLB_WORD0_SIZE_4KB 0x00000010
585 #define TLB_WORD0_SIZE_16KB 0x00000020
586 #define TLB_WORD0_SIZE_64KB 0x00000030
587 #define TLB_WORD0_SIZE_256KB 0x00000040
588 #define TLB_WORD0_SIZE_1MB 0x00000050
589 #define TLB_WORD0_SIZE_16MB 0x00000070
590 #define TLB_WORD0_SIZE_256MB 0x00000090
591 #define TLB_WORD0_TPAR_MASK 0x0000000F
592 #define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
593 #define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
595 #define TLB_WORD1_RPN_MASK 0xFFFFFC00
596 #define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
597 #define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
598 #define TLB_WORD1_PAR1_MASK 0x00000300
599 #define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
600 #define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
601 #define TLB_WORD1_PAR1_0 0x00000000
602 #define TLB_WORD1_PAR1_1 0x00000100
603 #define TLB_WORD1_PAR1_2 0x00000200
604 #define TLB_WORD1_PAR1_3 0x00000300
605 #define TLB_WORD1_ERPN_MASK 0x0000000F
606 #define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
607 #define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
609 #define TLB_WORD2_PAR2_MASK 0xC0000000
610 #define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
611 #define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
612 #define TLB_WORD2_PAR2_0 0x00000000
613 #define TLB_WORD2_PAR2_1 0x40000000
614 #define TLB_WORD2_PAR2_2 0x80000000
615 #define TLB_WORD2_PAR2_3 0xC0000000
616 #define TLB_WORD2_U0_MASK 0x00008000
617 #define TLB_WORD2_U0_ENABLE 0x00008000
618 #define TLB_WORD2_U0_DISABLE 0x00000000
619 #define TLB_WORD2_U1_MASK 0x00004000
620 #define TLB_WORD2_U1_ENABLE 0x00004000
621 #define TLB_WORD2_U1_DISABLE 0x00000000
622 #define TLB_WORD2_U2_MASK 0x00002000
623 #define TLB_WORD2_U2_ENABLE 0x00002000
624 #define TLB_WORD2_U2_DISABLE 0x00000000
625 #define TLB_WORD2_U3_MASK 0x00001000
626 #define TLB_WORD2_U3_ENABLE 0x00001000
627 #define TLB_WORD2_U3_DISABLE 0x00000000
628 #define TLB_WORD2_W_MASK 0x00000800
629 #define TLB_WORD2_W_ENABLE 0x00000800
630 #define TLB_WORD2_W_DISABLE 0x00000000
631 #define TLB_WORD2_I_MASK 0x00000400
632 #define TLB_WORD2_I_ENABLE 0x00000400
633 #define TLB_WORD2_I_DISABLE 0x00000000
634 #define TLB_WORD2_M_MASK 0x00000200
635 #define TLB_WORD2_M_ENABLE 0x00000200
636 #define TLB_WORD2_M_DISABLE 0x00000000
637 #define TLB_WORD2_G_MASK 0x00000100
638 #define TLB_WORD2_G_ENABLE 0x00000100
639 #define TLB_WORD2_G_DISABLE 0x00000000
640 #define TLB_WORD2_E_MASK 0x00000080
641 #define TLB_WORD2_E_ENABLE 0x00000080
642 #define TLB_WORD2_E_DISABLE 0x00000000
643 #define TLB_WORD2_UX_MASK 0x00000020
644 #define TLB_WORD2_UX_ENABLE 0x00000020
645 #define TLB_WORD2_UX_DISABLE 0x00000000
646 #define TLB_WORD2_UW_MASK 0x00000010
647 #define TLB_WORD2_UW_ENABLE 0x00000010
648 #define TLB_WORD2_UW_DISABLE 0x00000000
649 #define TLB_WORD2_UR_MASK 0x00000008
650 #define TLB_WORD2_UR_ENABLE 0x00000008
651 #define TLB_WORD2_UR_DISABLE 0x00000000
652 #define TLB_WORD2_SX_MASK 0x00000004
653 #define TLB_WORD2_SX_ENABLE 0x00000004
654 #define TLB_WORD2_SX_DISABLE 0x00000000
655 #define TLB_WORD2_SW_MASK 0x00000002
656 #define TLB_WORD2_SW_ENABLE 0x00000002
657 #define TLB_WORD2_SW_DISABLE 0x00000000
658 #define TLB_WORD2_SR_MASK 0x00000001
659 #define TLB_WORD2_SR_ENABLE 0x00000001
660 #define TLB_WORD2_SR_DISABLE 0x00000000
662 /*----------------------------------------------------------------------------+
663 | Following instructions are not available in Book E mode of the GNU assembler.
664 +----------------------------------------------------------------------------*/
665 #define DCCCI(ra,rb) .long 0x7c000000|\
666 (ra<<16)|(rb<<11)|(454<<1)
668 #define ICCCI(ra,rb) .long 0x7c000000|\
669 (ra<<16)|(rb<<11)|(966<<1)
671 #define DCREAD(rt,ra,rb) .long 0x7c000000|\
672 (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
674 #define ICREAD(ra,rb) .long 0x7c000000|\
675 (ra<<16)|(rb<<11)|(998<<1)
677 #define TLBSX(rt,ra,rb) .long 0x7c000000|\
678 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
680 #define TLBWE(rs,ra,ws) .long 0x7c000000|\
681 (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
683 #define TLBRE(rt,ra,ws) .long 0x7c000000|\
684 (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
686 #define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
687 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
689 #define MSYNC .long 0x7c000000|\
692 #define MBAR_INST .long 0x7c000000|\
697 void mttlb1(unsigned long index, unsigned long value);
698 void mttlb2(unsigned long index, unsigned long value);
699 void mttlb3(unsigned long index, unsigned long value);
700 unsigned long mftlb1(unsigned long index);
701 unsigned long mftlb2(unsigned long index);
702 unsigned long mftlb3(unsigned long index);
704 void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
705 void remove_tlb(u32 vaddr, u32 size);
706 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
707 #endif /* __ASSEMBLY__ */
709 #endif /* CONFIG_440 */
710 #endif /* _PPC_MMU_H_ */