2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860 ADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
10 /* ------------------------------------------------------------------------- */
12 #ifndef _CONFIG_ADS860_H
13 #define _CONFIG_ADS860_H
16 * High Level Configuration Options
19 #include <mpc8xx_irq.h>
21 #define CONFIG_MPC860 1
22 #define CONFIG_MPC860T 1
25 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
26 #undef CONFIG_8xx_CONS_SMC2
27 #undef CONFIG_8xx_CONS_NONE
28 #define CONFIG_BAUDRATE 19200 /* console baudrate */
29 #define CONFIG_PCMCIA 1 /* To enable PCMCIA support */
31 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
32 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
33 #define CFG_I2C_SLAVE 0x7F
35 #define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */
36 #define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */
37 /* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
39 #define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
41 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
44 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #undef CONFIG_BOOTARGS
50 #define CONFIG_BOOTCOMMAND \
52 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
53 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
56 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
57 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
59 #undef CONFIG_WATCHDOG /* watchdog disabled */
61 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
64 #if 0 /* private command defs */
65 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C | \
66 CFG_CMD_IDE | CFG_CMD_PCMCIA)
68 /* default command defs */
69 #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
71 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
72 #include <cmd_confdefs.h>
76 * Miscellaneous configurable options
78 #undef CFG_LONGHELP /* undef to save memory */
79 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
80 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
81 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
83 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
85 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
86 #define CFG_MAXARGS 16 /* max number of command args */
87 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
89 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
90 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
92 #define CFG_LOAD_ADDR 0x00100000
94 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
96 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
99 * Low Level Configuration Settings
100 * (address mappings, register initial values, etc.)
101 * You should know what you are doing if you make changes here.
103 /*-----------------------------------------------------------------------
104 * Internal Memory Mapped Register
106 #define CFG_IMMR 0xfff00000
107 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
109 /*-----------------------------------------------------------------------
110 * Definitions for initial stack pointer and data area (in DPRAM)
112 #define CFG_INIT_RAM_ADDR CFG_IMMR
113 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
114 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
115 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
116 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
118 /*-----------------------------------------------------------------------
119 * Start addresses for the final memory configuration
120 * (Set up by the startup code)
121 * Please note that CFG_SDRAM_BASE _must_ start at 0
123 #define CFG_SDRAM_BASE 0x00000000
124 #define CFG_SRAM_BASE 0x00000000
125 #define CFG_FLASH_BASE 0xfe000000
126 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
128 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
129 #define CFG_MONITOR_BASE CFG_FLASH_BASE
130 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
133 * For booting Linux, the board info and command line data
134 * have to be in the first 8 MB of memory, since this is
135 * the maximum mapped by the Linux kernel during initialization.
137 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
138 /*-----------------------------------------------------------------------
141 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
142 #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
144 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
145 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
147 #undef CFG_ENV_IS_IN_NVRAM
148 #undef CFG_ENV_IS_IN_EEPROM
149 #define CFG_ENV_IS_IN_FLASH 1
151 #define CFG_ENV_OFFSET 0x00040000
152 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
153 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
155 /* the other CS:s are determined by looking at parameters in BCSRx */
157 /*-----------------------------------------------------------------------
158 * Cache Configuration
160 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
161 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
162 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
165 /*-----------------------------------------------------------------------
166 * SYPCR - System Protection Control 11-9
167 * SYPCR can only be written once after reset!
168 *-----------------------------------------------------------------------
169 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
171 #if defined(CONFIG_WATCHDOG)
172 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
173 SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
175 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
178 /*-----------------------------------------------------------------------
179 * SUMCR - SIU Module Configuration 11-6
180 *-----------------------------------------------------------------------
181 * PCMCIA config., multi-function pin tri-state
183 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
185 /*-----------------------------------------------------------------------
186 * TBSCR - Time Base Status and Control 11-26
187 *-----------------------------------------------------------------------
188 * Clear Reference Interrupt Status, Timebase freezing enabled
190 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
192 /*-----------------------------------------------------------------------
193 * PISCR - Periodic Interrupt Status and Control 11-31
194 *-----------------------------------------------------------------------
195 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
197 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
199 /*-----------------------------------------------------------------------
200 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
201 *-----------------------------------------------------------------------
202 * set the PLL, the low-power modes and the reset control (15-29)
204 #define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
205 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
207 /*-----------------------------------------------------------------------
208 * SCCR - System Clock and reset Control Register 15-27
209 *-----------------------------------------------------------------------
210 * Set clock output, timebase and RTC source and divider,
211 * power management and some other internal clocks
213 #define SCCR_MASK SCCR_EBDF11
214 #define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
215 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
216 SCCR_DFLCD000 | SCCR_DFALCD00)
219 /*-----------------------------------------------------------------------
221 *-----------------------------------------------------------------------
226 /* Because of the way the 860 starts up and assigns CS0 the
227 * entire address space, we have to set the memory controller
228 * differently. Normally, you write the option register
229 * first, and then enable the chip select by writing the
230 * base register. For CS0, you must write the base register
231 * first, followed by the option register.
235 * Init Memory Controller:
237 * BR0/1 and OR0/1 (FLASH)
239 /* the other CS:s are determined by looking at parameters in BCSRx */
241 #define BCSR_ADDR ((uint) 0xff010000)
242 #define BCSR_SIZE ((uint)(64 * 1024))
244 #define FLASH_BASE0_PRELIM 0xfe000000 /* FLASH bank #0 */
245 #define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
247 #define CFG_REMAP_OR_AM 0xff000000 /* OR addr mask */
248 #define CFG_PRELIM_OR_AM 0xffe00000 /* OR addr mask */
250 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
251 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
253 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
255 #ifdef USE_REAL_FLASH_VALUES
257 * These values fit our FADS860T ...
258 * The "default" behaviour with 1Mbyte initial doesn't work for us!
260 #define CFG_BR0_PRELIM 0x0fe000001 /* Real values for the board */
261 #define CFG_OR0_PRELIM 0x0ffe00d34
262 #define CFG_BR2_PRELIM 0x000000081
263 #define CFG_OR2_PRELIM 0x0ff000800
265 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
266 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
269 /* BCSRx - Board Control and Status Registers */
270 /* #define CFG_OR1_REMAP CFG_OR0_REMAP */
271 #define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
272 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
275 * Memory Periodic Timer Prescaler
278 /* periodic timer for refresh */
279 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
281 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
282 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
283 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
285 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
286 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
287 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
290 * MAMR settings for SDRAM
294 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
295 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
296 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
298 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
299 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
300 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
302 #define CFG_MAMR 0x13a01114
304 * Internal Definitions
308 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
309 #define BOOTFLAG_WARM 0x02 /* Software reboot */
312 /* values according to the manual */
313 #define BCSR0 ((uint) (BCSR_ADDR + 00))
314 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
315 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
316 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
317 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
320 /*-----------------------------------------------------------------------
322 *-----------------------------------------------------------------------
325 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
326 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
327 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
328 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
329 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
330 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
331 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
332 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
335 /*-----------------------------------------------------------------------
337 *-----------------------------------------------------------------------
339 #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
340 #undef CONFIG_IDE_LED /* LED for ide supported */
341 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
343 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
344 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
346 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
347 #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
349 /* #define CFG_ATA_BASE_ADDR 0xFE100000 */
350 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
351 #define CFG_ATA_IDE0_OFFSET 0x0000
353 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
354 #define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
355 #define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
358 /* (F)ADS bitvalues by Helmut Buchsbaum
359 * see MPC8xxADS User's Manual for a proper description
360 * of the following structures
363 #define BCSR0_ERB ((uint)0x80000000)
364 #define BCSR0_IP ((uint)0x40000000)
365 #define BCSR0_BDIS ((uint)0x10000000)
366 #define BCSR0_BPS_MASK ((uint)0x0C000000)
367 #define BCSR0_ISB_MASK ((uint)0x01800000)
368 #define BCSR0_DBGC_MASK ((uint)0x00600000)
369 #define BCSR0_DBPC_MASK ((uint)0x00180000)
370 #define BCSR0_EBDF_MASK ((uint)0x00060000)
372 #define BCSR1_FLASH_EN ((uint)0x80000000)
373 #define BCSR1_DRAM_EN ((uint)0x40000000)
374 #define BCSR1_ETHEN ((uint)0x20000000)
375 #define BCSR1_IRDEN ((uint)0x10000000)
376 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
377 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
378 #define BCSR1_BCSR_EN ((uint)0x02000000)
379 #define BCSR1_RS232EN_1 ((uint)0x01000000)
380 #define BCSR1_PCCEN ((uint)0x00800000)
381 #define BCSR1_PCCVCC0 ((uint)0x00400000)
382 #define BCSR1_PCCVCCON BCSR1_PCCVCC0
383 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
384 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
385 #define BCSR1_RS232EN_2 ((uint)0x00040000)
386 #define BCSR1_SDRAM_EN ((uint)0x00020000)
387 #define BCSR1_PCCVCC1 ((uint)0x00010000)
389 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
390 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
391 #define BCSR2_DRAM_PD_SHIFT (23)
392 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
393 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
395 #define BCSR3_DBID_MASK ((ushort)0x3800)
396 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
397 #define BCSR3_BREVNR0 ((ushort)0x0080)
398 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
399 #define BCSR3_BREVN1 ((ushort)0x0008)
400 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
402 #define BCSR4_ETHLOOP ((uint)0x80000000)
403 #define BCSR4_TFPLDL ((uint)0x40000000)
404 #define BCSR4_TPSQEL ((uint)0x20000000)
405 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
407 #define BCSR4_USB_EN ((uint)0x08000000)
408 #endif /* CONFIG_MPC823 */
409 #ifdef CONFIG_MPC860SAR
410 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
411 #endif /* CONFIG_MPC860SAR */
412 #ifdef CONFIG_MPC860T
413 #define BCSR4_FETH_EN ((uint)0x08000000)
414 #endif /* CONFIG_MPC860T */
416 #define BCSR4_USB_SPEED ((uint)0x04000000)
417 #endif /* CONFIG_MPC823 */
418 #ifdef CONFIG_MPC860T
419 #define BCSR4_FETHCFG0 ((uint)0x04000000)
420 #endif /* CONFIG_MPC860T */
422 #define BCSR4_VCCO ((uint)0x02000000)
423 #endif /* CONFIG_MPC823 */
424 #ifdef CONFIG_MPC860T
425 #define BCSR4_FETHFDE ((uint)0x02000000)
426 #endif /* CONFIG_MPC860T */
428 #define BCSR4_VIDEO_ON ((uint)0x00800000)
429 #endif /* CONFIG_MPC823 */
431 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
432 #endif /* CONFIG_MPC823 */
433 #ifdef CONFIG_MPC860T
434 #define BCSR4_FETHCFG1 ((uint)0x00400000)
435 #endif /* CONFIG_MPC860T */
437 #define BCSR4_VIDEO_RST ((uint)0x00200000)
438 #endif /* CONFIG_MPC823 */
439 #ifdef CONFIG_MPC860T
440 #define BCSR4_FETHRST ((uint)0x00200000)
441 #endif /* CONFIG_MPC860T */
443 #define BCSR4_MODEM_EN ((uint)0x00100000)
444 #endif /* CONFIG_MPC823 */
446 #define BCSR4_DATA_VOICE ((uint)0x00080000)
447 #endif /* CONFIG_MPC823 */
449 #define BCSR4_DATA_VOICE ((uint)0x00080000)
450 #endif /* CONFIG_MPC850 */
452 #define CONFIG_DRAM_50MHZ 1
453 #define CONFIG_SDRAM_50MHZ
455 #ifdef CONFIG_MPC860T
456 /* Interrupt level assignments.
458 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
459 #endif /* CONFIG_MPC860T */
461 /* We don't use the 8259.
463 #define NR_8259_INTS 0
467 #define _MACH_8xx (_MACH_ads)
470 #define CONFIG_DISK_SPINUP_TIME 1000000
472 #undef CONFIG_DISK_SPINUP_TIME /* usinĀ“ Compact Flash */
475 /* PCMCIA configuration
477 #define PCMCIA_MAX_SLOTS 2
479 #define PCMCIA_SLOT_A 1
482 #endif /* _CONFIG_ADS860_H */