2 * AMIRIX.h: AMIRIX specific config options
4 * Author : Frank Smith (smith at amirix dot com)
6 * Derived from : other configuration header files in this tree
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License (GPL) version 2, incorporated herein by
10 * reference. Drivers based on or derived from this code fall under the GPL
11 * and must retain the authorship, copyright and this license notice. This
12 * file is not a complete program and may only be used when the entire
13 * program is licensed under the GPL.
21 * High Level Configuration Options
27 #define CONFIG_405 1 /* This is a PPC405 CPU */
28 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
30 #define CONFIG_AP1000 1 /* ...on an AP1000 board */
34 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
35 #define CFG_PROMPT "0> "
36 #define CFG_PROMPT_HUSH_PS2 "> "
38 #define CONFIG_COMMAND_EDIT 1
39 #define CONFIG_COMMAND_HISTORY 1
40 #define CONFIG_COMPLETE_ADDRESSES 1
42 #define CFG_ENV_IS_IN_FLASH 1
43 #define CFG_FLASH_USE_BUFFER_WRITE
45 #ifdef CFG_ENV_IS_IN_NVRAM
46 #undef CFG_ENV_IS_IN_FLASH
48 #ifdef CFG_ENV_IS_IN_FLASH
49 #undef CFG_ENV_IS_IN_NVRAM
53 #define CONFIG_BAUDRATE 57600
54 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
56 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
58 /* Size (bytes) of interrupt driven serial port buffer.
59 * Set to 0 to use polling instead of interrupts.
60 * Setting to 0 will also disable RTS/CTS handshaking.
62 #undef CONFIG_SERIAL_SOFTWARE_FIFO
64 #define CONFIG_BOOTARGS "console=ttyS0,57600"
66 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
67 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
71 #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & \
72 (~CFG_CMD_RTC) & ~(CFG_CMD_I2C)) | \
82 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
83 #include <cmd_confdefs.h>
85 #undef CONFIG_WATCHDOG /* watchdog disabled */
87 #define CONFIG_SYS_CLK_FREQ 30000000
89 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
92 * Miscellaneous configurable options
94 #define CFG_LONGHELP /* undef to save memory */
95 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
96 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
98 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
100 /* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
101 #define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */
102 #define CFG_MAXARGS 16 /* max number of command args */
103 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
105 #define CFG_ALT_MEMTEST 1
106 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
107 #define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
110 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
111 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
112 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
113 * The Linux BASE_BAUD define should match this configuration.
114 * baseBaud = cpuClock/(uartDivisor*16)
115 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
116 * set Linux BASE_BAUD to 403200.
118 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
119 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
121 #define CFG_NS16550_CLK 40000000
122 #define CFG_DUART_CHAN 0
123 #define CFG_NS16550_COM1 (0x4C000000 + 0x1000)
124 #define CFG_NS16550_COM2 (0x4C800000 + 0x1000)
125 #define CFG_NS16550_REG_SIZE 4
126 #define CFG_NS16550 1
127 #define CFG_INIT_CHAN1 1
128 #define CFG_INIT_CHAN2 0
130 /* The following table includes the supported baudrates */
131 #define CFG_BAUDRATE_TABLE \
132 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
134 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
135 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
137 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
141 /*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
144 * Please note that CFG_SDRAM_BASE _must_ start at 0
146 #define CFG_SDRAM_BASE 0x00000000
147 #define CFG_FLASH_BASE 0x20000000
148 #define CFG_MONITOR_BASE TEXT_BASE
149 #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
150 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
157 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
158 /*-----------------------------------------------------------------------
161 #define CFG_FLASH_CFI 1
162 #define CFG_PROGFLASH_BASE CFG_FLASH_BASE
163 #define CFG_CONFFLASH_BASE 0x24000000
165 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
166 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
168 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
169 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
171 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
173 /* BEG ENVIRONNEMENT FLASH */
174 #ifdef CFG_ENV_IS_IN_FLASH
175 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
176 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
177 #define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */
179 /* END ENVIRONNEMENT FLASH */
180 /*-----------------------------------------------------------------------
183 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
184 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
186 #ifdef CFG_ENV_IS_IN_NVRAM
187 #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
188 #define CFG_ENV_ADDR \
189 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
191 /*-----------------------------------------------------------------------
192 * Cache Configuration
194 #define CFG_DCACHE_SIZE 16384
195 #define CFG_CACHELINE_SIZE 32
196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
197 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
201 * Init Memory Controller:
203 * BR0/1 and OR0/1 (FLASH)
206 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
207 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
210 /* Configuration Port location */
211 #define CONFIG_PORT_ADDR 0xF0000500
213 /*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area (in DPRAM)
217 #define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
218 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
219 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
220 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
221 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
223 /*-----------------------------------------------------------------------
224 * Definitions for Serial Presence Detect EEPROM address
225 * (to get SDRAM settings)
227 #define SPD_EEPROM_ADDRESS 0x50
230 * Internal Definitions
234 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
235 #define BOOTFLAG_WARM 0x02 /* Software reboot */
237 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
238 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
239 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
244 #define CFG_JFFS2_FIRST_BANK 0
245 #define CFG_JFFS2_NUM_BANKS 1
246 #define CFG_JFFS2_FIRST_SECTOR 1
248 #define CONFIG_NET_MULTI
251 #define CFG_ETH_DEV_FN 0x0800
252 #define CFG_ETH_IOBASE 0x31000000
253 #define CFG_ETH_MEMBASE 0x32000000
255 #endif /* __CONFIG_H */