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[u-boot] / include / configs / C29XPCIE.h
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * C29XPCIE board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_SPIFLASH
15 #define CONFIG_RAMBOOT_SPIFLASH
16 #define CONFIG_SYS_TEXT_BASE            0x11000000
17 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
18 #endif
19
20 #ifdef CONFIG_NAND
21 #ifdef CONFIG_TPL_BUILD
22 #define CONFIG_SPL_NAND_BOOT
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_NAND_INIT
25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
26 #define CONFIG_SPL_COMMON_INIT_DDR
27 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
28 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
31 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
32 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
34 #elif defined(CONFIG_SPL_BUILD)
35 #define CONFIG_SPL_INIT_MINIMAL
36 #define CONFIG_SPL_NAND_MINIMAL
37 #define CONFIG_SPL_FLUSH_IMAGE
38 #define CONFIG_SPL_TEXT_BASE            0xff800000
39 #define CONFIG_SPL_MAX_SIZE             8192
40 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
41 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
42 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
43 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
44 #endif
45 #define CONFIG_SPL_PAD_TO               0x20000
46 #define CONFIG_TPL_PAD_TO               0x20000
47 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
48 #define CONFIG_SYS_TEXT_BASE            0x11001000
49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
50 #endif
51
52 #ifndef CONFIG_SYS_TEXT_BASE
53 #define CONFIG_SYS_TEXT_BASE            0xeff40000
54 #endif
55
56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
57 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
58 #endif
59
60 #ifdef CONFIG_SPL_BUILD
61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
62 #else
63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
64 #endif
65
66 #ifdef CONFIG_SPL_BUILD
67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68 #endif
69
70 /* High Level Configuration Options */
71 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
72
73 #ifdef CONFIG_PCI
74 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
75 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
76 #define CONFIG_PCI_INDIRECT_BRIDGE
77 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
78 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
79
80 #define CONFIG_CMD_PCI
81
82 /*
83  * PCI Windows
84  * Memory space is mapped 1-1, but I/O space must start from 0.
85  */
86 /* controller 1, Slot 1, tgtid 1, Base address a000 */
87 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
88 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
89 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
90 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
91 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
92 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
93 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
94 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
95 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
96
97 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
98 #endif
99
100 #define CONFIG_TSEC_ENET
101 #define CONFIG_ENV_OVERWRITE
102
103 #define CONFIG_DDR_CLK_FREQ     100000000
104 #define CONFIG_SYS_CLK_FREQ     66666666
105
106 #define CONFIG_HWCONFIG
107
108 /*
109  * These can be toggled for performance analysis, otherwise use default.
110  */
111 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
112 #define CONFIG_BTB                      /* toggle branch predition */
113
114 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
115
116 #define CONFIG_ENABLE_36BIT_PHYS
117
118 #define CONFIG_ADDR_MAP                 1
119 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
120
121 #define CONFIG_SYS_MEMTEST_START        0x00200000
122 #define CONFIG_SYS_MEMTEST_END          0x00400000
123 #define CONFIG_PANIC_HANG
124
125 /* DDR Setup */
126 #define CONFIG_DDR_SPD
127 #define CONFIG_SYS_SPD_BUS_NUM          0
128 #define SPD_EEPROM_ADDRESS              0x50
129 #define CONFIG_SYS_DDR_RAW_TIMING
130
131 /* DDR ECC Setup*/
132 #define CONFIG_DDR_ECC
133 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
135
136 #define CONFIG_SYS_SDRAM_SIZE           512
137 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
138 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
139
140 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
141 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
142
143 #define CONFIG_SYS_CCSRBAR              0xffe00000
144 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
145
146 /* Platform SRAM setting  */
147 #define CONFIG_SYS_PLATFORM_SRAM_BASE   0xffb00000
148 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
149                         (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
150 #define CONFIG_SYS_PLATFORM_SRAM_SIZE   (512 << 10)
151
152 /*
153  * IFC Definitions
154  */
155 /* NOR Flash on IFC */
156 #define CONFIG_SYS_FLASH_BASE           0xec000000
157 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
158
159 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
160
161 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
162 #define CONFIG_SYS_MAX_FLASH_BANKS      1
163
164 #define CONFIG_SYS_FLASH_QUIET_TEST
165 #define CONFIG_FLASH_SHOW_PROGRESS      45
166 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* in ms */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* in ms */
168
169 /* 16Bit NOR Flash - S29GL512S10TFI01 */
170 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
171                                 CSPR_PORT_SIZE_16 | \
172                                 CSPR_MSEL_NOR | \
173                                 CSPR_V)
174 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64*1024*1024)
175 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
176
177 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
178                                 FTIM0_NOR_TEADC(0x5) | \
179                                 FTIM0_NOR_TEAHC(0x5))
180 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
181                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
182                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
183 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
184                                 FTIM2_NOR_TCH(0x4) | \
185                                 FTIM2_NOR_TWPH(0x0E) | \
186                                 FTIM2_NOR_TWP(0x1c))
187 #define CONFIG_SYS_NOR_FTIM3    0x0
188
189 /* CFI for NOR Flash */
190 #define CONFIG_FLASH_CFI_DRIVER
191 #define CONFIG_SYS_FLASH_CFI
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
194
195 /* NAND Flash on IFC */
196 #define CONFIG_NAND_FSL_IFC
197 #define CONFIG_SYS_NAND_BASE            0xff800000
198 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
199
200 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
201
202 #define CONFIG_SYS_MAX_NAND_DEVICE      1
203 #define CONFIG_CMD_NAND
204 #define CONFIG_SYS_NAND_BLOCK_SIZE      (1024 * 1024)
205
206 /* 8Bit NAND Flash - K9F1G08U0B */
207 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
208                                 | CSPR_PORT_SIZE_8 \
209                                 | CSPR_MSEL_NAND \
210                                 | CSPR_V)
211 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
212 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280      /* 640b */
213 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
214                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
215                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
216                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
217                                 | CSOR_NAND_PGS_8K      /* Page Size = 8K */ \
218                                 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
219                                 | CSOR_NAND_PB(128))    /*128 Pages Per Block*/
220 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x01) | \
221                                 FTIM0_NAND_TWP(0x0c)   | \
222                                 FTIM0_NAND_TWCHT(0x08) | \
223                                 FTIM0_NAND_TWH(0x06))
224 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x28) | \
225                                 FTIM1_NAND_TWBE(0x1d)  | \
226                                 FTIM1_NAND_TRR(0x08)   | \
227                                 FTIM1_NAND_TRP(0x0c))
228 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x0c) | \
229                                 FTIM2_NAND_TREH(0x0a) | \
230                                 FTIM2_NAND_TWHRE(0x18))
231 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x04))
232
233 #define CONFIG_SYS_NAND_DDR_LAW         11
234
235 /* Set up IFC registers for boot location NOR/NAND */
236 #ifdef CONFIG_NAND
237 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
238 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
239 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
240 #define CONFIG_SYS_CSOR0_EXT            CONFIG_SYS_NAND_OOBSIZE
241 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
242 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
243 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
244 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
245 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
246 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
247 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
248 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
249 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
250 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
251 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
252 #else
253 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
254 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
261 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
262 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
263 #define CONFIG_SYS_CSOR1_EXT            CONFIG_SYS_NAND_OOBSIZE
264 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
265 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
266 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
267 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
268 #endif
269
270 /* CPLD on IFC, selected by CS2 */
271 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
272 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull \
273                                         | CONFIG_SYS_CPLD_BASE)
274
275 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
276                                 | CSPR_PORT_SIZE_8 \
277                                 | CSPR_MSEL_GPCM \
278                                 | CSPR_V)
279 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
280 #define CONFIG_SYS_CSOR2        0x0
281 /* CPLD Timing parameters for IFC CS2 */
282 #define CONFIG_SYS_CS2_FTIM0    (FTIM0_GPCM_TACSE(0x0e) | \
283                                 FTIM0_GPCM_TEADC(0x0e) | \
284                                 FTIM0_GPCM_TEAHC(0x0e))
285 #define CONFIG_SYS_CS2_FTIM1    (FTIM1_GPCM_TACO(0x0e) | \
286                                 FTIM1_GPCM_TRAD(0x1f))
287 #define CONFIG_SYS_CS2_FTIM2    (FTIM2_GPCM_TCS(0x0e) | \
288                                 FTIM2_GPCM_TCH(0x8) | \
289                                 FTIM2_GPCM_TWP(0x1f))
290 #define CONFIG_SYS_CS2_FTIM3    0x0
291
292 #if defined(CONFIG_RAMBOOT_SPIFLASH)
293 #define CONFIG_SYS_RAMBOOT
294 #define CONFIG_SYS_EXTRA_ENV_RELOC
295 #endif
296
297 #define CONFIG_BOARD_EARLY_INIT_R
298
299 #define CONFIG_SYS_INIT_RAM_LOCK
300 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
301 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
302
303 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
304                                                 - GENERATED_GBL_DATA_SIZE)
305 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
306
307 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
308 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024 * 1024)
309
310 /*
311  * Config the L2 Cache as L2 SRAM
312  */
313 #if defined(CONFIG_SPL_BUILD)
314 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
315 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
316 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
317 #define CONFIG_SYS_L2_SIZE              (256 << 10)
318 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
319 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
320 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
321 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
322 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
323 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
324 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
325 #elif defined(CONFIG_NAND)
326 #ifdef CONFIG_TPL_BUILD
327 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
328 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
329 #define CONFIG_SYS_L2_SIZE              (256 << 10)
330 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
331 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
332 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
333 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
334 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
335 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
336 #else
337 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
338 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
339 #define CONFIG_SYS_L2_SIZE              (256 << 10)
340 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
341 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
342 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
343 #endif
344 #endif
345 #endif
346
347 /* Serial Port */
348 #define CONFIG_CONS_INDEX       1
349 #define CONFIG_SYS_NS16550_SERIAL
350 #define CONFIG_SYS_NS16550_REG_SIZE     1
351 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
352
353 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
354 #define CONFIG_NS16550_MIN_FUNCTIONS
355 #endif
356
357 #define CONFIG_SYS_BAUDRATE_TABLE       \
358         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
359
360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
362
363 #define CONFIG_SYS_I2C
364 #define CONFIG_SYS_I2C_FSL
365 #define CONFIG_SYS_FSL_I2C_SPEED        400000
366 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
367 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
368 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
369 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
370 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
371
372 /* I2C EEPROM */
373 /* enable read and write access to EEPROM */
374 #define CONFIG_CMD_EEPROM
375 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
376 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
377 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
378
379 /* eSPI - Enhanced SPI */
380 #define CONFIG_SF_DEFAULT_SPEED         10000000
381 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
382
383 #ifdef CONFIG_TSEC_ENET
384 #define CONFIG_MII                      /* MII PHY management */
385 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
386 #define CONFIG_TSEC1            1
387 #define CONFIG_TSEC1_NAME       "eTSEC1"
388 #define CONFIG_TSEC2            1
389 #define CONFIG_TSEC2_NAME       "eTSEC2"
390
391 /* Default mode is RGMII mode */
392 #define TSEC1_PHY_ADDR          0
393 #define TSEC2_PHY_ADDR          2
394
395 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
396 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
397
398 #define CONFIG_ETHPRIME         "eTSEC1"
399
400 #define CONFIG_PHY_GIGE
401 #endif  /* CONFIG_TSEC_ENET */
402
403 /*
404  * Environment
405  */
406 #if defined(CONFIG_SYS_RAMBOOT)
407 #if defined(CONFIG_RAMBOOT_SPIFLASH)
408 #define CONFIG_ENV_IS_IN_SPI_FLASH
409 #define CONFIG_ENV_SPI_BUS      0
410 #define CONFIG_ENV_SPI_CS       0
411 #define CONFIG_ENV_SPI_MAX_HZ   10000000
412 #define CONFIG_ENV_SPI_MODE     0
413 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
414 #define CONFIG_ENV_SECT_SIZE    0x10000
415 #define CONFIG_ENV_SIZE         0x2000
416 #endif
417 #elif defined(CONFIG_NAND)
418 #define CONFIG_ENV_IS_IN_NAND
419 #ifdef CONFIG_TPL_BUILD
420 #define CONFIG_ENV_SIZE         0x2000
421 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
422 #else
423 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
424 #define CONFIG_ENV_RANGE        CONFIG_ENV_SIZE
425 #endif
426 #define CONFIG_ENV_OFFSET       CONFIG_SYS_NAND_BLOCK_SIZE
427 #else
428 #define CONFIG_ENV_IS_IN_FLASH
429 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
430 #define CONFIG_ENV_SIZE         0x2000
431 #define CONFIG_ENV_SECT_SIZE    0x20000
432 #endif
433
434 #define CONFIG_LOADS_ECHO
435 #define CONFIG_SYS_LOADS_BAUD_CHANGE
436
437 /*
438  * Command line configuration.
439  */
440 #define CONFIG_CMD_ERRATA
441 #define CONFIG_CMD_IRQ
442 #define CONFIG_CMD_REGINFO
443
444 /* Hash command with SHA acceleration supported in hardware */
445 #ifdef CONFIG_FSL_CAAM
446 #define CONFIG_CMD_HASH
447 #define CONFIG_SHA_HW_ACCEL
448 #endif
449
450 /*
451  * Miscellaneous configurable options
452  */
453 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
454 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
455 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
456 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
457
458 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
459 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
460                                                 /* Print Buffer Size */
461 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
462 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
463
464 /*
465  * For booting Linux, the board info and command line data
466  * have to be in the first 64 MB of memory, since this is
467  * the maximum mapped by the Linux kernel during initialization.
468  */
469 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
470 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
471
472 /*
473  * Environment Configuration
474  */
475
476 #ifdef CONFIG_TSEC_ENET
477 #define CONFIG_HAS_ETH0
478 #define CONFIG_HAS_ETH1
479 #endif
480
481 #define CONFIG_ROOTPATH         "/opt/nfsroot"
482 #define CONFIG_BOOTFILE         "uImage"
483 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
484
485 /* default location for tftp and bootm */
486 #define CONFIG_LOADADDR         1000000
487
488
489 #define CONFIG_BAUDRATE         115200
490
491 #define CONFIG_DEF_HWCONFIG     fsl_ddr:ecc=on
492
493 #define CONFIG_EXTRA_ENV_SETTINGS                               \
494         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
495         "netdev=eth0\0"                                         \
496         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
497         "loadaddr=1000000\0"                            \
498         "consoledev=ttyS0\0"                            \
499         "ramdiskaddr=2000000\0"                         \
500         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
501         "fdtaddr=1e00000\0"                             \
502         "fdtfile=name/of/device-tree.dtb\0"                     \
503         "othbootargs=ramdisk_size=600000\0"             \
504
505 #define CONFIG_RAMBOOTCOMMAND                   \
506         "setenv bootargs root=/dev/ram rw "     \
507         "console=$consoledev,$baudrate $othbootargs; "  \
508         "tftp $ramdiskaddr $ramdiskfile;"       \
509         "tftp $loadaddr $bootfile;"             \
510         "tftp $fdtaddr $fdtfile;"               \
511         "bootm $loadaddr $ramdiskaddr $fdtaddr"
512
513 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
514
515 #include <asm/fsl_secure_boot.h>
516
517 #endif  /* __CONFIG_H */