2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * C29XPCIE board configuration file
14 #define CONFIG_DISPLAY_BOARDINFO
16 #ifdef CONFIG_C29XPCIE
17 #define CONFIG_PPC_C29X
20 #ifdef CONFIG_SPIFLASH
21 #define CONFIG_RAMBOOT_SPIFLASH
22 #define CONFIG_SYS_TEXT_BASE 0x11000000
23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #ifdef CONFIG_TPL_BUILD
28 #define CONFIG_SPL_NAND_BOOT
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_NAND_INIT
31 #define CONFIG_TPL_SERIAL_SUPPORT
32 #define CONFIG_TPL_LIBGENERIC_SUPPORT
33 #define CONFIG_TPL_LIBCOMMON_SUPPORT
34 #define CONFIG_TPL_I2C_SUPPORT
35 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
36 #define CONFIG_TPL_NAND_SUPPORT
37 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT
38 #define CONFIG_SPL_COMMON_INIT_DDR
39 #define CONFIG_SPL_MAX_SIZE (128 << 10)
40 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
42 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
43 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
44 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
45 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
46 #elif defined(CONFIG_SPL_BUILD)
47 #define CONFIG_SPL_INIT_MINIMAL
48 #define CONFIG_SPL_SERIAL_SUPPORT
49 #define CONFIG_SPL_NAND_SUPPORT
50 #define CONFIG_SPL_NAND_MINIMAL
51 #define CONFIG_SPL_FLUSH_IMAGE
52 #define CONFIG_SPL_TEXT_BASE 0xff800000
53 #define CONFIG_SPL_MAX_SIZE 8192
54 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
55 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
56 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
59 #define CONFIG_SPL_PAD_TO 0x20000
60 #define CONFIG_TPL_PAD_TO 0x20000
61 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
62 #define CONFIG_SYS_TEXT_BASE 0x11001000
63 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
66 #ifndef CONFIG_SYS_TEXT_BASE
67 #define CONFIG_SYS_TEXT_BASE 0xeff40000
70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
71 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74 #ifdef CONFIG_SPL_BUILD
75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
77 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
80 #ifdef CONFIG_SPL_BUILD
81 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
84 /* High Level Configuration Options */
85 #define CONFIG_BOOKE /* BOOKE */
86 #define CONFIG_E500 /* BOOKE e500 family */
87 #define CONFIG_FSL_IFC /* Enable IFC Support */
88 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
89 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
91 #define CONFIG_PCI /* Enable PCI/PCIE */
93 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
94 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
95 #define CONFIG_PCI_INDIRECT_BRIDGE
96 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
97 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
99 #define CONFIG_CMD_PCI
103 * Memory space is mapped 1-1, but I/O space must start from 0.
105 /* controller 1, Slot 1, tgtid 1, Base address a000 */
106 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
107 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
108 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
109 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
110 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
111 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
112 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
113 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
114 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
116 #define CONFIG_PCI_PNP /* do pci plug-and-play */
118 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
119 #define CONFIG_DOS_PARTITION
122 #define CONFIG_FSL_LAW /* Use common FSL init code */
123 #define CONFIG_TSEC_ENET
124 #define CONFIG_ENV_OVERWRITE
126 #define CONFIG_DDR_CLK_FREQ 100000000
127 #define CONFIG_SYS_CLK_FREQ 66666666
129 #define CONFIG_HWCONFIG
132 * These can be toggled for performance analysis, otherwise use default.
134 #define CONFIG_L2_CACHE /* toggle L2 cache */
135 #define CONFIG_BTB /* toggle branch predition */
137 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
139 #define CONFIG_ENABLE_36BIT_PHYS
141 #define CONFIG_ADDR_MAP 1
142 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
144 #define CONFIG_SYS_MEMTEST_START 0x00200000
145 #define CONFIG_SYS_MEMTEST_END 0x00400000
146 #define CONFIG_PANIC_HANG
149 #define CONFIG_SYS_FSL_DDR3
150 #define CONFIG_DDR_SPD
151 #define CONFIG_SYS_SPD_BUS_NUM 0
152 #define SPD_EEPROM_ADDRESS 0x50
153 #define CONFIG_SYS_DDR_RAW_TIMING
156 #define CONFIG_DDR_ECC
157 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
158 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
160 #define CONFIG_SYS_SDRAM_SIZE 512
161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
164 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
165 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
167 #define CONFIG_SYS_CCSRBAR 0xffe00000
168 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
170 /* Platform SRAM setting */
171 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
172 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
173 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
174 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
176 #ifdef CONFIG_SPL_BUILD
177 #define CONFIG_SYS_NO_FLASH
183 /* NOR Flash on IFC */
184 #define CONFIG_SYS_FLASH_BASE 0xec000000
185 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
187 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
189 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
190 #define CONFIG_SYS_MAX_FLASH_BANKS 1
192 #define CONFIG_SYS_FLASH_QUIET_TEST
193 #define CONFIG_FLASH_SHOW_PROGRESS 45
194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
197 /* 16Bit NOR Flash - S29GL512S10TFI01 */
198 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
199 CSPR_PORT_SIZE_16 | \
202 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
203 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
205 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
206 FTIM0_NOR_TEADC(0x5) | \
207 FTIM0_NOR_TEAHC(0x5))
208 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
209 FTIM1_NOR_TRAD_NOR(0x1A) |\
210 FTIM1_NOR_TSEQRAD_NOR(0x13))
211 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
212 FTIM2_NOR_TCH(0x4) | \
213 FTIM2_NOR_TWPH(0x0E) | \
215 #define CONFIG_SYS_NOR_FTIM3 0x0
217 /* CFI for NOR Flash */
218 #define CONFIG_FLASH_CFI_DRIVER
219 #define CONFIG_SYS_FLASH_CFI
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
223 /* NAND Flash on IFC */
224 #define CONFIG_NAND_FSL_IFC
225 #define CONFIG_SYS_NAND_BASE 0xff800000
226 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
228 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
230 #define CONFIG_SYS_MAX_NAND_DEVICE 1
231 #define CONFIG_CMD_NAND
232 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
234 /* 8Bit NAND Flash - K9F1G08U0B */
235 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
239 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
240 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
241 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
242 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
243 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
244 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
245 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
246 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
247 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
248 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
249 FTIM0_NAND_TWP(0x0c) | \
250 FTIM0_NAND_TWCHT(0x08) | \
251 FTIM0_NAND_TWH(0x06))
252 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
253 FTIM1_NAND_TWBE(0x1d) | \
254 FTIM1_NAND_TRR(0x08) | \
255 FTIM1_NAND_TRP(0x0c))
256 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
257 FTIM2_NAND_TREH(0x0a) | \
258 FTIM2_NAND_TWHRE(0x18))
259 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
261 #define CONFIG_SYS_NAND_DDR_LAW 11
263 /* Set up IFC registers for boot location NOR/NAND */
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
268 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
269 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
281 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
282 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
283 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
284 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
285 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
286 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
287 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
289 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
290 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
291 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
292 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
293 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
294 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
295 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
298 /* CPLD on IFC, selected by CS2 */
299 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
300 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
301 | CONFIG_SYS_CPLD_BASE)
303 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
307 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
308 #define CONFIG_SYS_CSOR2 0x0
309 /* CPLD Timing parameters for IFC CS2 */
310 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
311 FTIM0_GPCM_TEADC(0x0e) | \
312 FTIM0_GPCM_TEAHC(0x0e))
313 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
314 FTIM1_GPCM_TRAD(0x1f))
315 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
316 FTIM2_GPCM_TCH(0x8) | \
317 FTIM2_GPCM_TWP(0x1f))
318 #define CONFIG_SYS_CS2_FTIM3 0x0
320 #if defined(CONFIG_RAMBOOT_SPIFLASH)
321 #define CONFIG_SYS_RAMBOOT
322 #define CONFIG_SYS_EXTRA_ENV_RELOC
325 #define CONFIG_BOARD_EARLY_INIT_R
327 #define CONFIG_SYS_INIT_RAM_LOCK
328 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
329 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
331 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
332 - GENERATED_GBL_DATA_SIZE)
333 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
335 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
336 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
339 * Config the L2 Cache as L2 SRAM
341 #if defined(CONFIG_SPL_BUILD)
342 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
343 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
344 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
345 #define CONFIG_SYS_L2_SIZE (256 << 10)
346 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
347 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
348 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
349 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
350 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
351 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
352 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
353 #elif defined(CONFIG_NAND)
354 #ifdef CONFIG_TPL_BUILD
355 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
356 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
357 #define CONFIG_SYS_L2_SIZE (256 << 10)
358 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
359 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
360 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
361 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
362 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
363 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
365 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
366 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
367 #define CONFIG_SYS_L2_SIZE (256 << 10)
368 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
369 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
370 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
376 #define CONFIG_CONS_INDEX 1
377 #define CONFIG_SYS_NS16550_SERIAL
378 #define CONFIG_SYS_NS16550_REG_SIZE 1
379 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
381 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
382 #define CONFIG_NS16550_MIN_FUNCTIONS
385 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
387 #define CONFIG_SYS_BAUDRATE_TABLE \
388 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
390 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
391 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
393 #define CONFIG_SYS_I2C
394 #define CONFIG_SYS_I2C_FSL
395 #define CONFIG_SYS_FSL_I2C_SPEED 400000
396 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
397 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
398 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
399 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
403 /* enable read and write access to EEPROM */
404 #define CONFIG_CMD_EEPROM
405 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
406 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
407 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
409 /* eSPI - Enhanced SPI */
410 #define CONFIG_SF_DEFAULT_SPEED 10000000
411 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
413 #ifdef CONFIG_TSEC_ENET
414 #define CONFIG_MII /* MII PHY management */
415 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
416 #define CONFIG_TSEC1 1
417 #define CONFIG_TSEC1_NAME "eTSEC1"
418 #define CONFIG_TSEC2 1
419 #define CONFIG_TSEC2_NAME "eTSEC2"
421 /* Default mode is RGMII mode */
422 #define TSEC1_PHY_ADDR 0
423 #define TSEC2_PHY_ADDR 2
425 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
426 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
428 #define CONFIG_ETHPRIME "eTSEC1"
430 #define CONFIG_PHY_GIGE
431 #endif /* CONFIG_TSEC_ENET */
436 #if defined(CONFIG_SYS_RAMBOOT)
437 #if defined(CONFIG_RAMBOOT_SPIFLASH)
438 #define CONFIG_ENV_IS_IN_SPI_FLASH
439 #define CONFIG_ENV_SPI_BUS 0
440 #define CONFIG_ENV_SPI_CS 0
441 #define CONFIG_ENV_SPI_MAX_HZ 10000000
442 #define CONFIG_ENV_SPI_MODE 0
443 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
444 #define CONFIG_ENV_SECT_SIZE 0x10000
445 #define CONFIG_ENV_SIZE 0x2000
447 #elif defined(CONFIG_NAND)
448 #define CONFIG_ENV_IS_IN_NAND
449 #ifdef CONFIG_TPL_BUILD
450 #define CONFIG_ENV_SIZE 0x2000
451 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
453 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
454 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
456 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
458 #define CONFIG_ENV_IS_IN_FLASH
459 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
460 #define CONFIG_ENV_SIZE 0x2000
461 #define CONFIG_ENV_SECT_SIZE 0x20000
464 #define CONFIG_LOADS_ECHO
465 #define CONFIG_SYS_LOADS_BAUD_CHANGE
468 * Command line configuration.
470 #define CONFIG_CMD_ERRATA
471 #define CONFIG_CMD_IRQ
472 #define CONFIG_CMD_REGINFO
474 /* Hash command with SHA acceleration supported in hardware */
475 #ifdef CONFIG_FSL_CAAM
476 #define CONFIG_CMD_HASH
477 #define CONFIG_SHA_HW_ACCEL
481 * Miscellaneous configurable options
483 #define CONFIG_SYS_LONGHELP /* undef to save memory */
484 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
485 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
486 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
488 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
489 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
490 /* Print Buffer Size */
491 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
495 * For booting Linux, the board info and command line data
496 * have to be in the first 64 MB of memory, since this is
497 * the maximum mapped by the Linux kernel during initialization.
499 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
500 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
503 * Environment Configuration
506 #ifdef CONFIG_TSEC_ENET
507 #define CONFIG_HAS_ETH0
508 #define CONFIG_HAS_ETH1
511 #define CONFIG_ROOTPATH "/opt/nfsroot"
512 #define CONFIG_BOOTFILE "uImage"
513 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
515 /* default location for tftp and bootm */
516 #define CONFIG_LOADADDR 1000000
519 #define CONFIG_BAUDRATE 115200
521 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
523 #define CONFIG_EXTRA_ENV_SETTINGS \
524 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
526 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
527 "loadaddr=1000000\0" \
528 "consoledev=ttyS0\0" \
529 "ramdiskaddr=2000000\0" \
530 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
531 "fdtaddr=1e00000\0" \
532 "fdtfile=name/of/device-tree.dtb\0" \
533 "othbootargs=ramdisk_size=600000\0" \
535 #define CONFIG_RAMBOOTCOMMAND \
536 "setenv bootargs root=/dev/ram rw " \
537 "console=$consoledev,$baudrate $othbootargs; " \
538 "tftp $ramdiskaddr $ramdiskfile;" \
539 "tftp $loadaddr $bootfile;" \
540 "tftp $fdtaddr $fdtfile;" \
541 "bootm $loadaddr $ramdiskaddr $fdtaddr"
543 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
545 #include <asm/fsl_secure_boot.h>
547 #endif /* __CONFIG_H */