2 * (C) Copyright 2004 DENX Software Engineering,
3 * Wolfgang Grandegger <wg@denx.de>
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
11 * Credits: Stefan Roese, Wolfgang Denk
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * board/config.h - configuration options, board specific
36 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
37 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
38 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
39 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
40 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
46 #undef __DEBUG_START_FROM_SRAM__
47 #define __DISABLE_MACHINE_EXCEPTION__
49 #ifdef __DEBUG_START_FROM_SRAM__
50 #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
54 * High Level Configuration Options
58 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
59 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
60 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
62 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
63 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
65 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
67 #define CONFIG_UART1_CONSOLE 1 /* Use second UART */
68 #define CONFIG_BAUDRATE 115200
69 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71 #undef CONFIG_BOOTARGS
74 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
75 #define CONFIG_ETHADDR 00:50:C2:1E:AF:FC
76 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FB
78 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
84 #define CONFIG_MII 1 /* MII PHY management */
85 #ifndef CONFIG_EXT_PHY
86 #define CONFIG_PHY_ADDR 1 /* PHY address */
88 #define CONFIG_PHY_ADDR 2 /* PHY address */
90 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
92 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
102 #define CONFIG_MAC_PARTITION
103 #define CONFIG_DOS_PARTITION
105 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106 #include <cmd_confdefs.h>
108 #undef CONFIG_WATCHDOG /* watchdog disabled */
110 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
111 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
113 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
116 * Miscellaneous configurable options
118 #define CFG_LONGHELP /* undef to save memory */
119 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
121 #undef CFG_HUSH_PARSER /* use "hush" command parser */
122 #ifdef CFG_HUSH_PARSER
123 #define CFG_PROMPT_HUSH_PS2 "> "
126 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
127 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
129 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
131 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
132 #define CFG_MAXARGS 16 /* max number of command args */
133 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
135 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
137 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
139 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
140 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
142 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
143 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
144 #define CFG_BASE_BAUD 691200
146 /* The following table includes the supported baudrates */
147 #define CFG_BAUDRATE_TABLE \
148 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
149 57600, 115200, 230400, 460800, 921600 }
151 #define CFG_LOAD_ADDR 0x100000 /* default load address */
152 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
154 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
156 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
158 /*-----------------------------------------------------------------------
160 *-----------------------------------------------------------------------
162 #define CFG_NAND0_BASE 0xFF400000
163 #define CFG_NAND1_BASE 0xFF000000
165 /* For CATcenter there is only NAND on the module */
166 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
167 #define SECTORSIZE 512
170 #define ADDR_COLUMN 1
172 #define ADDR_COLUMN_PAGE 3
174 #define NAND_ChipID_UNKNOWN 0x00
175 #define NAND_MAX_FLOORS 1
176 #define NAND_MAX_CHIPS 1
178 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
179 #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
180 #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
181 #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
183 #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
184 #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
185 #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
186 #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
189 #define NAND_DISABLE_CE(nand) do \
191 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
193 case CFG_NAND0_BASE: \
194 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
196 case CFG_NAND1_BASE: \
197 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
202 #define NAND_ENABLE_CE(nand) do \
204 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
206 case CFG_NAND0_BASE: \
207 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
209 case CFG_NAND1_BASE: \
210 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
216 #define NAND_CTL_CLRALE(nandptr) do \
218 switch((unsigned long)nandptr) \
220 case CFG_NAND0_BASE: \
221 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
223 case CFG_NAND1_BASE: \
224 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
229 #define NAND_CTL_SETALE(nandptr) do \
231 switch((unsigned long)nandptr) \
233 case CFG_NAND0_BASE: \
234 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
236 case CFG_NAND1_BASE: \
237 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
242 #define NAND_CTL_CLRCLE(nandptr) do \
244 switch((unsigned long)nandptr) \
246 case CFG_NAND0_BASE: \
247 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
249 case CFG_NAND1_BASE: \
250 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
255 #define NAND_CTL_SETCLE(nandptr) do { \
256 switch((unsigned long)nandptr) { \
257 case CFG_NAND0_BASE: \
258 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
260 case CFG_NAND1_BASE: \
261 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
267 /* constant delay (see also tR in the datasheet) */
268 #define NAND_WAIT_READY(nand) do { \
272 /* use the R/B pin */
276 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
277 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
278 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
279 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
281 /*-----------------------------------------------------------------------
283 *-----------------------------------------------------------------------
285 #if 0 /* No PCI on CATcenter */
286 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
287 #define PCI_HOST_FORCE 1 /* configure as pci host */
288 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
290 #define CONFIG_PCI /* include pci support */
291 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
292 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
293 /* resource configuration */
295 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
297 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
298 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
299 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
300 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
301 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
302 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
303 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
304 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
305 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
308 /*-----------------------------------------------------------------------
309 * Start addresses for the final memory configuration
310 * (Set up by the startup code)
311 * Please note that CFG_SDRAM_BASE _must_ start at 0
313 #define CFG_SDRAM_BASE 0x00000000
314 #define CFG_FLASH_BASE 0xFFFC0000
315 #define CFG_MONITOR_BASE CFG_FLASH_BASE
316 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
317 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
320 * For booting Linux, the board info and command line data
321 * have to be in the first 8 MB of memory, since this is
322 * the maximum mapped by the Linux kernel during initialization.
324 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
325 /*-----------------------------------------------------------------------
328 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
329 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
331 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
332 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
334 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
335 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
336 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
338 * The following defines are added for buggy IOP480 byte interface.
339 * All other boards should use the standard values (CPCI405 etc.)
341 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
342 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
343 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
345 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
347 #if 0 /* test-only */
348 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
349 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
352 /*-----------------------------------------------------------------------
353 * Environment Variable setup
355 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
356 #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
357 #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
358 #define CFG_ENV_ADDR_REDUND 0xFFFFA000
359 #define CFG_ENV_SIZE_REDUND 0x2000
361 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
362 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
364 /*-----------------------------------------------------------------------
365 * I2C EEPROM (CAT24WC16) for environment
367 #define CONFIG_HARD_I2C /* I2c with hardware support */
368 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
369 #define CFG_I2C_SLAVE 0x7F
371 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
372 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
373 /* mask of address bits that overflow into the "EEPROM chip address" */
374 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
375 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
376 /* 16 byte page write mode using*/
377 /* last 4 bits of the address */
378 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
379 #define CFG_EEPROM_PAGE_WRITE_ENABLE
381 /*-----------------------------------------------------------------------
382 * Cache Configuration
384 #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
385 /* have only 8kB, 16kB is save here */
386 #define CFG_CACHELINE_SIZE 32 /* ... */
387 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
388 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
392 * Init Memory Controller:
394 * BR0/1 and OR0/1 (FLASH)
397 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
399 /*-----------------------------------------------------------------------
400 * External Bus Controller (EBC) Setup
403 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
404 #define CFG_EBC_PB0AP 0x92015480
405 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
407 /* Memory Bank 1 (External SRAM) initialization */
408 /* Since this must replace NOR Flash, we use the same settings for CS0 */
409 #define CFG_EBC_PB1AP 0x92015480
410 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
412 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
413 #define CFG_EBC_PB2AP 0x92015480
414 #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
416 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
417 #define CFG_EBC_PB3AP 0x92015480
418 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
422 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
423 #define CFG_EBC_PB1AP 0x92015480
424 #define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
426 /* Memory Bank 2 (CAN0, 1) initialization */
427 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
428 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
430 /* Memory Bank 3 (CompactFlash IDE) initialization */
431 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
432 #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
434 /* Memory Bank 4 (NVRAM/RTC) initialization */
435 #define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
436 #define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
439 /*-----------------------------------------------------------------------
442 /* FPGA internal regs */
443 #define CFG_FPGA_MODE 0x00
444 #define CFG_FPGA_STATUS 0x02
445 #define CFG_FPGA_TS 0x04
446 #define CFG_FPGA_TS_LOW 0x06
447 #define CFG_FPGA_TS_CAP0 0x10
448 #define CFG_FPGA_TS_CAP0_LOW 0x12
449 #define CFG_FPGA_TS_CAP1 0x14
450 #define CFG_FPGA_TS_CAP1_LOW 0x16
451 #define CFG_FPGA_TS_CAP2 0x18
452 #define CFG_FPGA_TS_CAP2_LOW 0x1a
453 #define CFG_FPGA_TS_CAP3 0x1c
454 #define CFG_FPGA_TS_CAP3_LOW 0x1e
457 #define CFG_FPGA_MODE_CF_RESET 0x0001
458 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
459 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
460 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
462 /* FPGA Status Reg */
463 #define CFG_FPGA_STATUS_DIP0 0x0001
464 #define CFG_FPGA_STATUS_DIP1 0x0002
465 #define CFG_FPGA_STATUS_DIP2 0x0004
466 #define CFG_FPGA_STATUS_FLASH 0x0008
467 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
469 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
470 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
472 /* FPGA program pin configuration */
473 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
474 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
475 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
476 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
477 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
479 /*-----------------------------------------------------------------------
480 * Definitions for initial stack pointer and data area (in data cache)
482 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
483 #define CFG_TEMP_STACK_OCM 1
485 /* On Chip Memory location */
486 #define CFG_OCM_DATA_ADDR 0xF8000000
487 #define CFG_OCM_DATA_SIZE 0x1000
488 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
489 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
491 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
492 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
493 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
495 /*-----------------------------------------------------------------------
496 * Definitions for GPIO setup (PPC405EP specific)
498 * GPIO0[0] - External Bus Controller BLAST output
499 * GPIO0[1-9] - Instruction trace outputs -> GPIO
500 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
501 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
502 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
503 * GPIO0[24-27] - UART0 control signal inputs/outputs
504 * GPIO0[28-29] - UART1 data signal input/output
505 * GPIO0[30] - EMAC0 input
506 * GPIO0[31] - EMAC1 reject packet as output
508 #define CFG_GPIO0_OSRH 0x40000550
509 #define CFG_GPIO0_OSRL 0x00000110
510 #define CFG_GPIO0_ISR1H 0x00000000
511 /*#define CFG_GPIO0_ISR1L 0x15555445*/
512 #define CFG_GPIO0_ISR1L 0x15555444
513 #define CFG_GPIO0_TSRH 0x00000000
514 #define CFG_GPIO0_TSRL 0x00000000
515 #define CFG_GPIO0_TCR 0xF7FF8014
518 * Internal Definitions
522 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
523 #define BOOTFLAG_WARM 0x02 /* Software reboot */
526 #define CONFIG_NO_SERIAL_EEPROM
528 /*--------------------------------------------------------------------*/
530 #ifdef CONFIG_NO_SERIAL_EEPROM
533 !-----------------------------------------------------------------------
534 ! Defines for entry options.
535 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
536 ! are plugged in the board will be utilized as non-ECC DIMMs.
537 !-----------------------------------------------------------------------
539 #undef AUTO_MEMORY_CONFIG
540 #define DIMM_READ_ADDR 0xAB
541 #define DIMM_WRITE_ADDR 0xAA
544 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
545 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
546 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
547 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
548 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
549 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
550 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
551 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
552 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
553 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
555 /* Defines for CPC0_PLLMR1 Register fields */
556 #define PLL_ACTIVE 0x80000000
557 #define CPC0_PLLMR1_SSCS 0x80000000
558 #define PLL_RESET 0x40000000
559 #define CPC0_PLLMR1_PLLR 0x40000000
560 /* Feedback multiplier */
561 #define PLL_FBKDIV 0x00F00000
562 #define CPC0_PLLMR1_FBDV 0x00F00000
563 #define PLL_FBKDIV_16 0x00000000
564 #define PLL_FBKDIV_1 0x00100000
565 #define PLL_FBKDIV_2 0x00200000
566 #define PLL_FBKDIV_3 0x00300000
567 #define PLL_FBKDIV_4 0x00400000
568 #define PLL_FBKDIV_5 0x00500000
569 #define PLL_FBKDIV_6 0x00600000
570 #define PLL_FBKDIV_7 0x00700000
571 #define PLL_FBKDIV_8 0x00800000
572 #define PLL_FBKDIV_9 0x00900000
573 #define PLL_FBKDIV_10 0x00A00000
574 #define PLL_FBKDIV_11 0x00B00000
575 #define PLL_FBKDIV_12 0x00C00000
576 #define PLL_FBKDIV_13 0x00D00000
577 #define PLL_FBKDIV_14 0x00E00000
578 #define PLL_FBKDIV_15 0x00F00000
579 /* Forward A divisor */
580 #define PLL_FWDDIVA 0x00070000
581 #define CPC0_PLLMR1_FWDVA 0x00070000
582 #define PLL_FWDDIVA_8 0x00000000
583 #define PLL_FWDDIVA_7 0x00010000
584 #define PLL_FWDDIVA_6 0x00020000
585 #define PLL_FWDDIVA_5 0x00030000
586 #define PLL_FWDDIVA_4 0x00040000
587 #define PLL_FWDDIVA_3 0x00050000
588 #define PLL_FWDDIVA_2 0x00060000
589 #define PLL_FWDDIVA_1 0x00070000
590 /* Forward B divisor */
591 #define PLL_FWDDIVB 0x00007000
592 #define CPC0_PLLMR1_FWDVB 0x00007000
593 #define PLL_FWDDIVB_8 0x00000000
594 #define PLL_FWDDIVB_7 0x00001000
595 #define PLL_FWDDIVB_6 0x00002000
596 #define PLL_FWDDIVB_5 0x00003000
597 #define PLL_FWDDIVB_4 0x00004000
598 #define PLL_FWDDIVB_3 0x00005000
599 #define PLL_FWDDIVB_2 0x00006000
600 #define PLL_FWDDIVB_1 0x00007000
602 #define PLL_TUNE_MASK 0x000003FF
603 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
604 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
605 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
606 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
607 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
608 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
609 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
611 /* Defines for CPC0_PLLMR0 Register fields */
613 #define PLL_CPUDIV 0x00300000
614 #define CPC0_PLLMR0_CCDV 0x00300000
615 #define PLL_CPUDIV_1 0x00000000
616 #define PLL_CPUDIV_2 0x00100000
617 #define PLL_CPUDIV_3 0x00200000
618 #define PLL_CPUDIV_4 0x00300000
620 #define PLL_PLBDIV 0x00030000
621 #define CPC0_PLLMR0_CBDV 0x00030000
622 #define PLL_PLBDIV_1 0x00000000
623 #define PLL_PLBDIV_2 0x00010000
624 #define PLL_PLBDIV_3 0x00020000
625 #define PLL_PLBDIV_4 0x00030000
627 #define PLL_OPBDIV 0x00003000
628 #define CPC0_PLLMR0_OPDV 0x00003000
629 #define PLL_OPBDIV_1 0x00000000
630 #define PLL_OPBDIV_2 0x00001000
631 #define PLL_OPBDIV_3 0x00002000
632 #define PLL_OPBDIV_4 0x00003000
634 #define PLL_EXTBUSDIV 0x00000300
635 #define CPC0_PLLMR0_EPDV 0x00000300
636 #define PLL_EXTBUSDIV_2 0x00000000
637 #define PLL_EXTBUSDIV_3 0x00000100
638 #define PLL_EXTBUSDIV_4 0x00000200
639 #define PLL_EXTBUSDIV_5 0x00000300
641 #define PLL_MALDIV 0x00000030
642 #define CPC0_PLLMR0_MPDV 0x00000030
643 #define PLL_MALDIV_1 0x00000000
644 #define PLL_MALDIV_2 0x00000010
645 #define PLL_MALDIV_3 0x00000020
646 #define PLL_MALDIV_4 0x00000030
648 #define PLL_PCIDIV 0x00000003
649 #define CPC0_PLLMR0_PPFD 0x00000003
650 #define PLL_PCIDIV_1 0x00000000
651 #define PLL_PCIDIV_2 0x00000001
652 #define PLL_PCIDIV_3 0x00000002
653 #define PLL_PCIDIV_4 0x00000003
655 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
656 #define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
657 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
658 PLL_MALDIV_1 | PLL_PCIDIV_4)
659 #define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
660 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
661 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
662 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
663 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
664 PLL_MALDIV_1 | PLL_PCIDIV_4)
665 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
666 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
667 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
668 #define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
669 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
670 PLL_MALDIV_1 | PLL_PCIDIV_4)
671 #define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
672 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
673 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
674 #define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
675 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
676 PLL_MALDIV_1 | PLL_PCIDIV_2)
677 #define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
678 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
679 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
681 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
683 #define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55
684 #define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55
686 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
687 #define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33
688 #define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33
690 /* Model BA (default) */
691 #define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33
692 #define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33
695 #endif /* CONFIG_NO_SERIAL_EEPROM */
697 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
698 #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
699 #define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
700 #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
701 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
703 #endif /* __CONFIG_H */