3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * CMS700.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
21 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
22 #define CONFIG_VOM405 1 /* ...on a VOM405 board */
24 #define CONFIG_SYS_TEXT_BASE 0xFFFC8000
26 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
27 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
29 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
31 #define CONFIG_BAUDRATE 9600
32 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
34 #undef CONFIG_BOOTARGS
35 #undef CONFIG_BOOTCOMMAND
37 #define CONFIG_PREBOOT /* enable preboot variable */
39 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
41 #define CONFIG_PPC4xx_EMAC
42 #undef CONFIG_HAS_ETH1
44 #define CONFIG_MII 1 /* MII PHY management */
45 #define CONFIG_PHY_ADDR 0 /* PHY address */
46 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
47 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
52 #define CONFIG_BOOTP_SUBNETMASK
53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME
55 #define CONFIG_BOOTP_BOOTPATH
56 #define CONFIG_BOOTP_DNS
57 #define CONFIG_BOOTP_DNS2
58 #define CONFIG_BOOTP_SEND_HOSTNAME
62 * Command line configuration.
64 #include <config_cmd_default.h>
66 #define CONFIG_CMD_DHCP
67 #define CONFIG_CMD_BSP
68 #define CONFIG_CMD_ELF
69 #define CONFIG_CMD_NAND
70 #define CONFIG_CMD_I2C
71 #define CONFIG_CMD_DATE
72 #define CONFIG_CMD_MII
73 #define CONFIG_CMD_PING
74 #define CONFIG_CMD_EEPROM
77 #undef CONFIG_WATCHDOG /* watchdog disabled */
79 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
81 #undef CONFIG_PRAM /* no "protected RAM" */
84 * Miscellaneous configurable options
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
88 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
90 #if defined(CONFIG_CMD_KGDB)
91 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
99 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
101 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
103 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
104 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
106 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
107 #define CONFIG_SYS_NS16550
108 #define CONFIG_SYS_NS16550_SERIAL
109 #define CONFIG_SYS_NS16550_REG_SIZE 1
110 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
112 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
113 #define CONFIG_SYS_BASE_BAUD 691200
115 /* The following table includes the supported baudrates */
116 #define CONFIG_SYS_BAUDRATE_TABLE \
117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
118 57600, 115200, 230400, 460800, 921600 }
120 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
123 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
125 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
127 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
129 /*-----------------------------------------------------------------------
131 *-----------------------------------------------------------------------
133 #define CONFIG_RTC_DS1337
134 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
136 /*-----------------------------------------------------------------------
138 *-----------------------------------------------------------------------
140 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
142 #define NAND_BIG_DELAY_US 25
144 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
145 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
146 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
147 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
149 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
150 #define CONFIG_SYS_NAND_QUIET 1
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
157 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
158 /*-----------------------------------------------------------------------
161 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
169 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
170 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
171 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
173 * The following defines are added for buggy IOP480 byte interface.
174 * All other boards should use the standard values (CPCI405 etc.)
176 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
177 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
178 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
180 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
182 /*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
187 #define CONFIG_SYS_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
191 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
193 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
194 # define CONFIG_SYS_RAMBOOT 1
196 # undef CONFIG_SYS_RAMBOOT
199 /*-----------------------------------------------------------------------
200 * Environment Variable setup
202 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
203 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
204 #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
205 /* total size of a CAT24WC16 is 2048 bytes */
207 /*-----------------------------------------------------------------------
208 * I2C EEPROM (CAT24WC16) for environment
210 #define CONFIG_SYS_I2C
211 #define CONFIG_SYS_I2C_PPC4XX
212 #define CONFIG_SYS_I2C_PPC4XX_CH0
213 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
214 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
218 /* mask of address bits that overflow into the "EEPROM chip address" */
219 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
221 /* 16 byte page write mode using*/
222 /* last 4 bits of the address */
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
225 #define CONFIG_SYS_EEPROM_WREN 1
227 /*-----------------------------------------------------------------------
228 * External Bus Controller (EBC) Setup
230 #define CONFIG_SYS_PLD_BASE 0xf0000000
231 #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
233 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
234 #define CONFIG_SYS_EBC_PB0AP 0x92015480
235 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
237 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
238 #define CONFIG_SYS_EBC_PB1AP 0x92015480
239 #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
241 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
242 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
243 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
245 /*-----------------------------------------------------------------------
248 #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
250 /* FPGA program pin configuration */
251 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
252 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
253 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
254 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
255 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
257 /*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in data cache)
260 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
261 #define CONFIG_SYS_TEMP_STACK_OCM 1
263 /* On Chip Memory location */
264 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
265 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
266 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
267 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
269 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
270 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
272 /*-----------------------------------------------------------------------
273 * Definitions for GPIO setup (PPC405EP specific)
275 * GPIO0[0] - External Bus Controller BLAST output
276 * GPIO0[1-9] - Instruction trace outputs -> GPIO
277 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
278 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
279 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
280 * GPIO0[24-27] - UART0 control signal inputs/outputs
281 * GPIO0[28-29] - UART1 data signal input/output
282 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
284 /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
285 /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
286 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
287 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
288 #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
289 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
290 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
291 #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
292 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
293 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
294 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
296 #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
297 #define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
300 * Default speed selection (cpu_plb_opb_ebc) in mhz.
301 * This value will be set if iic boot eprom is disabled.
303 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
304 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
306 #endif /* __CONFIG_H */