3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39 #define CONFIG_CPCI405_VER2 1 /* ...version 2 */
41 #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49 #define CONFIG_PREBOOT \
50 "crc32 f0207004 ffc 0;" \
51 "if cmp 0 f0207000 1;" \
52 "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
53 "else;echo Old CRC is bad;fi"
56 #undef CONFIG_BOOTARGS
57 #define CONFIG_RAMBOOTCOMMAND \
58 "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
59 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
60 "bootm ffc00000 ffca0000"
61 #define CONFIG_NFSBOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
65 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
67 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
68 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
70 #define CONFIG_MII 1 /* MII PHY management */
71 #define CONFIG_PHY_ADDR 0 /* PHY address */
73 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
76 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
77 CONFIG_BOOTP_VENDOREX)
79 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT)
82 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
94 #define CONFIG_MAC_PARTITION
95 #define CONFIG_DOS_PARTITION
97 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
98 #include <cmd_confdefs.h>
100 #undef CONFIG_WATCHDOG /* watchdog disabled */
102 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
105 * Miscellaneous configurable options
107 #define CFG_LONGHELP /* undef to save memory */
108 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
110 #undef CFG_HUSH_PARSER /* use "hush" command parser */
111 #ifdef CFG_HUSH_PARSER
112 #define CFG_PROMPT_HUSH_PS2 "> "
115 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
116 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
118 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
120 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
121 #define CFG_MAXARGS 16 /* max number of command args */
122 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
124 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
126 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
128 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
129 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
131 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
132 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
133 #define CFG_BASE_BAUD 691200
135 /* The following table includes the supported baudrates */
136 #define CFG_BAUDRATE_TABLE \
137 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
138 57600, 115200, 230400, 460800, 921600 }
140 #define CFG_LOAD_ADDR 0x100000 /* default load address */
141 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
143 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
145 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
147 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
149 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
151 /*-----------------------------------------------------------------------
153 *-----------------------------------------------------------------------
155 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
156 #define PCI_HOST_FORCE 1 /* configure as pci host */
157 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
159 #define CONFIG_PCI /* include pci support */
160 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
161 #define CONFIG_PCI_PNP /* do pci plug-and-play */
162 /* resource configuration */
164 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
166 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
168 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
169 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
170 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
171 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
172 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
173 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
174 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
175 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
176 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
177 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
179 /*-----------------------------------------------------------------------
181 *-----------------------------------------------------------------------
183 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
184 #undef CONFIG_IDE_LED /* no led for ide supported */
185 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
187 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
188 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
190 #define CFG_ATA_BASE_ADDR 0xF0100000
191 #define CFG_ATA_IDE0_OFFSET 0x0000
193 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
194 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
195 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
197 /*-----------------------------------------------------------------------
198 * Start addresses for the final memory configuration
199 * (Set up by the startup code)
200 * Please note that CFG_SDRAM_BASE _must_ start at 0
202 #define CFG_SDRAM_BASE 0x00000000
203 #define CFG_FLASH_BASE 0xFFFC0000
204 #define CFG_MONITOR_BASE CFG_FLASH_BASE
205 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
206 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
213 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 /*-----------------------------------------------------------------------
217 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
218 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
220 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
223 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
224 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
225 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
227 * The following defines are added for buggy IOP480 byte interface.
228 * All other boards should use the standard values (CPCI405 etc.)
230 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
231 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
232 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
234 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
236 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
237 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
239 #if 0 /* Use NVRAM for environment variables */
240 /*-----------------------------------------------------------------------
243 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
244 #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
245 #define CFG_ENV_ADDR \
246 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
248 #else /* Use EEPROM for environment variables */
250 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
251 #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
252 #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
253 /* total size of a CAT24WC16 is 2048 bytes */
256 #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
257 #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
258 #define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
260 /*-----------------------------------------------------------------------
261 * I2C EEPROM (CAT24WC16) for environment
263 #define CONFIG_HARD_I2C /* I2c with hardware support */
264 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
265 #define CFG_I2C_SLAVE 0x7F
267 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
268 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
269 /* mask of address bits that overflow into the "EEPROM chip address" */
270 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
271 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
272 /* 16 byte page write mode using*/
273 /* last 4 bits of the address */
274 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
275 #define CFG_EEPROM_PAGE_WRITE_ENABLE
277 /*-----------------------------------------------------------------------
278 * Cache Configuration
280 #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
281 /* have only 8kB, 16kB is save here */
282 #define CFG_CACHELINE_SIZE 32 /* ... */
283 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
284 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
288 * Init Memory Controller:
290 * BR0/1 and OR0/1 (FLASH)
293 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
294 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
296 /*-----------------------------------------------------------------------
297 * External Bus Controller (EBC) Setup
300 /* Memory Bank 0 (Flash Bank 0) initialization */
301 #define CFG_EBC_PB0AP 0x92015480
302 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
304 /* Memory Bank 1 (Flash Bank 1) initialization */
305 #define CFG_EBC_PB1AP 0x92015480
306 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
308 /* Memory Bank 2 (CAN0, 1) initialization */
309 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
310 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
311 #define CFG_LED_ADDR 0xF0000380
313 /* Memory Bank 3 (CompactFlash IDE) initialization */
314 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
315 #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
317 /* Memory Bank 4 (NVRAM/RTC) initialization */
318 /*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
319 #define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
320 #define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
322 /* Memory Bank 5 (optional Quart) initialization */
323 #define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
324 #define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
326 /* Memory Bank 6 (FPGA internal) initialization */
327 #define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
328 #define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
329 #define CFG_FPGA_BASE_ADDR 0xF0400000
331 /*-----------------------------------------------------------------------
334 /* FPGA internal regs */
335 #define CFG_FPGA_MODE 0x00
336 #define CFG_FPGA_STATUS 0x02
337 #define CFG_FPGA_TS 0x04
338 #define CFG_FPGA_TS_LOW 0x06
339 #define CFG_FPGA_TS_CAP0 0x10
340 #define CFG_FPGA_TS_CAP0_LOW 0x12
341 #define CFG_FPGA_TS_CAP1 0x14
342 #define CFG_FPGA_TS_CAP1_LOW 0x16
343 #define CFG_FPGA_TS_CAP2 0x18
344 #define CFG_FPGA_TS_CAP2_LOW 0x1a
345 #define CFG_FPGA_TS_CAP3 0x1c
346 #define CFG_FPGA_TS_CAP3_LOW 0x1e
349 #define CFG_FPGA_MODE_CF_RESET 0x0001
350 #define CFG_FPGA_MODE_DUART_RESET 0x0002
351 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
352 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
353 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
354 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
356 /* FPGA Status Reg */
357 #define CFG_FPGA_STATUS_DIP0 0x0001
358 #define CFG_FPGA_STATUS_DIP1 0x0002
359 #define CFG_FPGA_STATUS_DIP2 0x0004
360 #define CFG_FPGA_STATUS_FLASH 0x0008
361 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
363 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
364 #define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
366 /* FPGA program pin configuration */
367 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
368 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
369 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
370 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
371 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
373 /*-----------------------------------------------------------------------
374 * Definitions for initial stack pointer and data area (in data cache)
376 #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
378 #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
379 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
380 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
381 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
382 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
386 * Internal Definitions
390 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
391 #define BOOTFLAG_WARM 0x02 /* Software reboot */
393 #endif /* __CONFIG_H */