2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_CPU86 1 /* ...on a CPU86 board */
38 #define CONFIG_CPM2 1 /* Has a CPM2 */
41 * select serial console configuration
43 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
44 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
47 * if CONFIG_CONS_NONE is defined, then the serial console routines must
48 * defined elsewhere (for example, on the cogent platform, there are serial
49 * ports on the motherboard which are used for the serial console - see
50 * cogent/cma101/serial.[ch]).
52 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
53 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
54 #undef CONFIG_CONS_NONE /* define if console on something else*/
55 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
57 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
58 #define CONFIG_BAUDRATE 230400
60 #define CONFIG_BAUDRATE 9600
64 * select ethernet configuration
66 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
70 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
71 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
73 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
74 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
75 #undef CONFIG_ETHER_NONE /* define if ether on something else */
76 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
78 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
83 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
84 * - Enable Full Duplex in FSMR
86 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
87 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
88 # define CFG_CPMFCR_RAMTYPE 0
89 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
91 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
96 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
97 * - Enable Full Duplex in FSMR
99 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
100 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
101 # define CFG_CPMFCR_RAMTYPE 0
102 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
104 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
106 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
107 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
109 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
111 #define CONFIG_PREBOOT \
113 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
116 #undef CONFIG_BOOTARGS
117 #define CONFIG_BOOTCOMMAND \
119 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
120 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
123 /*-----------------------------------------------------------------------
124 * I2C/EEPROM/RTC configuration
126 #define CONFIG_SOFT_I2C /* Software I2C support enabled */
128 # define CFG_I2C_SPEED 50000
129 # define CFG_I2C_SLAVE 0xFE
131 * Software (bit-bang) I2C driver configuration
133 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
134 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
135 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
136 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
137 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
138 else iop->pdat &= ~0x00010000
139 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
140 else iop->pdat &= ~0x00020000
141 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
143 #define CONFIG_RTC_PCF8563
144 #define CFG_I2C_RTC_ADDR 0x51
146 #undef CONFIG_WATCHDOG /* watchdog disabled */
148 /*-----------------------------------------------------------------------
149 * Disk-On-Chip configuration
152 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
154 #define CFG_DOC_SUPPORT_2000
155 #define CFG_DOC_SUPPORT_MILLENNIUM
157 /*-----------------------------------------------------------------------
158 * Miscellaneous configuration options
161 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
162 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
164 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
168 * Command line configuration.
170 #include <config_cmd_default.h>
172 #define CONFIG_CMD_BEDBUG
173 #define CONFIG_CMD_DATE
174 #define CONFIG_CMD_DHCP
175 #define CONFIG_CMD_DOC
176 #define CONFIG_CMD_EEPROM
177 #define CONFIG_CMD_I2C
178 #define CONFIG_CMD_NFS
179 #define CONFIG_CMD_SNTP
183 * Miscellaneous configurable options
185 #define CFG_LONGHELP /* undef to save memory */
186 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
187 #if defined(CONFIG_CMD_KGDB)
188 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
190 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
192 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
193 #define CFG_MAXARGS 16 /* max number of command args */
194 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
196 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
197 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
199 #define CFG_LOAD_ADDR 0x100000 /* default load address */
201 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
203 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
205 #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
212 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 /*-----------------------------------------------------------------------
215 * Flash configuration
218 #define CFG_BOOTROM_BASE 0xFF800000
219 #define CFG_BOOTROM_SIZE 0x00080000
220 #define CFG_FLASH_BASE 0xFF000000
221 #define CFG_FLASH_SIZE 0x00800000
223 /*-----------------------------------------------------------------------
226 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
227 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
229 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
230 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
232 /*-----------------------------------------------------------------------
233 * Other areas to be mapped
236 /* CS3: Dual ported SRAM */
237 #define CFG_DPSRAM_BASE 0x40000000
238 #define CFG_DPSRAM_SIZE 0x00020000
240 /* CS4: DiskOnChip */
241 #define CFG_DOC_BASE 0xF4000000
242 #define CFG_DOC_SIZE 0x00100000
244 /* CS5: FDC37C78 controller */
245 #define CFG_FDC37C78_BASE 0xF1000000
246 #define CFG_FDC37C78_SIZE 0x00100000
248 /* CS6: Board configuration registers */
249 #define CFG_BCRS_BASE 0xF2000000
250 #define CFG_BCRS_SIZE 0x00010000
252 /* CS7: VME Extended Access Range */
253 #define CFG_VMEEAR_BASE 0x80000000
254 #define CFG_VMEEAR_SIZE 0x01000000
256 /* CS8: VME Standard Access Range */
257 #define CFG_VMESAR_BASE 0xFE000000
258 #define CFG_VMESAR_SIZE 0x01000000
260 /* CS9: VME Short I/O Access Range */
261 #define CFG_VMESIOAR_BASE 0xFD000000
262 #define CFG_VMESIOAR_SIZE 0x01000000
264 /*-----------------------------------------------------------------------
265 * Hard Reset Configuration Words
267 * if you change bits in the HRCW, you must also change the CFG_*
268 * defines for the various registers affected by the HRCW e.g. changing
269 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
271 #if defined(CONFIG_BOOT_ROM)
272 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
273 HRCW_BPS01 | HRCW_CS10PC01)
275 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
278 /* no slaves so just fill with zeros */
279 #define CFG_HRCW_SLAVE1 0
280 #define CFG_HRCW_SLAVE2 0
281 #define CFG_HRCW_SLAVE3 0
282 #define CFG_HRCW_SLAVE4 0
283 #define CFG_HRCW_SLAVE5 0
284 #define CFG_HRCW_SLAVE6 0
285 #define CFG_HRCW_SLAVE7 0
287 /*-----------------------------------------------------------------------
288 * Internal Memory Mapped Register
290 #define CFG_IMMR 0xF0000000
292 /*-----------------------------------------------------------------------
293 * Definitions for initial stack pointer and data area (in DPRAM)
295 #define CFG_INIT_RAM_ADDR CFG_IMMR
296 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
297 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
298 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
299 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
301 /*-----------------------------------------------------------------------
302 * Start addresses for the final memory configuration
303 * (Set up by the startup code)
304 * Please note that CFG_SDRAM_BASE _must_ start at 0
306 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
308 #define CFG_SDRAM_BASE 0x00000000
309 #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
310 #define CFG_MONITOR_BASE TEXT_BASE
311 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
312 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
314 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
319 /* environment is in Flash */
320 #define CFG_ENV_IS_IN_FLASH 1
321 #ifdef CONFIG_BOOT_ROM
322 # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
323 # define CFG_ENV_SIZE 0x10000
324 # define CFG_ENV_SECT_SIZE 0x10000
327 /* environment is in EEPROM */
328 #define CFG_ENV_IS_IN_EEPROM 1
329 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
330 #define CFG_I2C_EEPROM_ADDR_LEN 1
331 /* mask of address bits that overflow into the "EEPROM chip address" */
332 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
333 #define CFG_EEPROM_PAGE_WRITE_BITS 4
334 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
335 #define CFG_ENV_OFFSET 512
336 #define CFG_ENV_SIZE (2048 - 512)
340 * Internal Definitions
344 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
345 #define BOOTFLAG_WARM 0x02 /* Software reboot */
348 /*-----------------------------------------------------------------------
349 * Cache Configuration
351 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
352 #if defined(CONFIG_CMD_KGDB)
353 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
356 /*-----------------------------------------------------------------------
357 * HIDx - Hardware Implementation-dependent Registers 2-11
358 *-----------------------------------------------------------------------
359 * HID0 also contains cache control - initially enable both caches and
360 * invalidate contents, then the final state leaves only the instruction
361 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
362 * but Soft reset does not.
364 * HID1 has only read-only information - nothing to set.
366 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
367 HID0_DCI|HID0_IFEM|HID0_ABE)
368 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
371 /*-----------------------------------------------------------------------
372 * RMR - Reset Mode Register 5-5
373 *-----------------------------------------------------------------------
374 * turn on Checkstop Reset Enable
376 #define CFG_RMR RMR_CSRE
378 /*-----------------------------------------------------------------------
379 * BCR - Bus Configuration 4-25
380 *-----------------------------------------------------------------------
382 #define BCR_APD01 0x10000000
383 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
385 /*-----------------------------------------------------------------------
386 * SIUMCR - SIU Module Configuration 4-31
387 *-----------------------------------------------------------------------
389 #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
390 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
392 /*-----------------------------------------------------------------------
393 * SYPCR - System Protection Control 4-35
394 * SYPCR can only be written once after reset!
395 *-----------------------------------------------------------------------
396 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
398 #if defined(CONFIG_WATCHDOG)
399 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
400 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
402 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
403 SYPCR_SWRI|SYPCR_SWP)
404 #endif /* CONFIG_WATCHDOG */
406 /*-----------------------------------------------------------------------
407 * TMCNTSC - Time Counter Status and Control 4-40
408 *-----------------------------------------------------------------------
409 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
410 * and enable Time Counter
412 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
414 /*-----------------------------------------------------------------------
415 * PISCR - Periodic Interrupt Status and Control 4-42
416 *-----------------------------------------------------------------------
417 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
420 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
422 /*-----------------------------------------------------------------------
423 * SCCR - System Clock Control 9-8
424 *-----------------------------------------------------------------------
425 * Ensure DFBRG is Divide by 16
427 #define CFG_SCCR SCCR_DFBRG01
429 /*-----------------------------------------------------------------------
430 * RCCR - RISC Controller Configuration 13-7
431 *-----------------------------------------------------------------------
435 #define CFG_MIN_AM_MASK 0xC0000000
436 /*-----------------------------------------------------------------------
437 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
438 *-----------------------------------------------------------------------
440 #define CFG_MPTPR 0x1F00
442 /*-----------------------------------------------------------------------
443 * PSRT - Refresh Timer Register 10-16
444 *-----------------------------------------------------------------------
446 #define CFG_PSRT 0x0f
448 /*-----------------------------------------------------------------------
449 * PSRT - SDRAM Mode Register 10-10
450 *-----------------------------------------------------------------------
453 /* SDRAM initialization values for 8-column chips
455 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
457 ORxS_ROWST_PBI0_A9 |\
460 #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
461 PSDMR_BSMA_A14_A16 |\
462 PSDMR_SDA10_PBI0_A10 |\
470 /* SDRAM initialization values for 9-column chips
472 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
474 ORxS_ROWST_PBI0_A7 |\
477 #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
478 PSDMR_BSMA_A13_A15 |\
479 PSDMR_SDA10_PBI0_A9 |\
488 * Init Memory Controller:
490 * Bank Bus Machine PortSz Device
491 * ---- --- ------- ------ ------
492 * 0 60x GPCM 8 bit Boot ROM
493 * 1 60x GPCM 64 bit FLASH
494 * 2 60x SDRAM 64 bit SDRAM
498 #define CFG_MRS_OFFS 0x00000000
500 #ifdef CONFIG_BOOT_ROM
503 #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
508 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
516 #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
521 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
527 #else /* CONFIG_BOOT_ROM */
530 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
535 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
543 #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
548 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
554 #endif /* CONFIG_BOOT_ROM */
557 /* Bank 2 - 60x bus SDRAM
560 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
565 #define CFG_OR2_PRELIM CFG_OR2_9COL
567 #define CFG_PSDMR CFG_PSDMR_9COL
568 #endif /* CFG_RAMBOOT */
570 /* Bank 3 - Dual Ported SRAM
572 #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
577 #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
583 /* Bank 4 - DiskOnChip
585 #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
590 #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
595 /* Bank 5 - FDC37C78 controller
597 #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
602 #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
607 /* Bank 6 - Board control registers
609 #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
614 #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
618 /* Bank 7 - VME Extended Access Range
620 #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
625 #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
631 /* Bank 8 - VME Standard Access Range
633 #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
638 #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
644 /* Bank 9 - VME Short I/O Access Range
646 #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
651 #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
657 #endif /* __CONFIG_H */