3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #include <asm/processor.h>
33 /* This define must be before the core.h include */
34 #define CONFIG_DB64460 1 /* this is an DB64460 board */
37 #include "../board/Marvell/include/core.h"
40 /*-----------------------------------------------------*/
41 /* #include "../board/db64460/local.h" */
45 #define CONFIG_ETHADDR 64:46:00:00:00:01
46 #define CONFIG_ETH1ADDR 64:46:00:00:00:02
47 #define CONFIG_ETH2ADDR 64:46:00:00:00:03
49 #define CONFIG_ENV_OVERWRITE
50 #endif /* __CONFIG_H */
53 * High Level Configuration Options
57 #define CONFIG_74xx /* we have a 750FX (override local.h) */
59 #define CONFIG_DB64460 1 /* this is an DB64460 board */
61 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
62 /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
63 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
64 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
66 #undef CONFIG_ECC /* enable ECC support */
67 #define CONFIG_MV64460_ECC
69 /* which initialization functions to call for this board */
70 #define CONFIG_MISC_INIT_R /* initialize the icache L1 */
71 #define CONFIG_BOARD_PRE_INIT
73 #define CFG_BOARD_NAME "DB64460"
74 #define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
76 /*#define CFG_HUSH_PARSER */
77 #undef CFG_HUSH_PARSER
79 #define CFG_PROMPT_HUSH_PS2 "> "
82 * The following defines let you select what serial you want to use
83 * for your console driver.
86 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
87 * cable onto the second DUART channel, change the CFG_DUART port from 1
90 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
91 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
94 #define CONFIG_MPSC_PORT 0
96 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
97 #define CONFIG_NET_MULTI
100 /* #undef CONFIG_ETHER_PORT_MII */
102 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
104 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
106 #define CONFIG_ZERO_BOOTDELAY_CHECK
109 #undef CONFIG_BOOTARGS
110 /*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
112 /* ronen - autoboot using tftp */
113 #if (CONFIG_BOOTDELAY >= 0)
114 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
115 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
116 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
118 #define CONFIG_BOOTARGS "console=ttyS0,115200"
122 /* ronen - the u-boot.bin should be ~0x30000 bytes */
123 #define CONFIG_EXTRA_ENV_SETTINGS \
124 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
125 cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
126 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
127 cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
128 "bootargs_root=root=/dev/nfs rw\0" \
129 "bootargs_end=:::DB64460:eth0:none \0"\
130 "ethprime=mv_enet0\0"\
131 "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
132 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
134 /* --------------------------------------------------------------------------------------------------------------- */
135 /* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
137 #define CONFIG_IPADDR 10.2.40.90
139 #define CONFIG_SERIAL "No. 1"
140 #define CONFIG_SERVERIP 10.2.1.126
141 #define CONFIG_ROOTPATH /mnt/yellow_dog_mini
144 #define CONFIG_TESTDRAMDATA y
145 #define CONFIG_TESTDRAMADDRESS n
146 #define CONFIG_TESETDRAMWALK n
148 /* --------------------------------------------------------------------------------------------------------------- */
150 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
151 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
153 #undef CONFIG_WATCHDOG /* watchdog disabled */
154 #undef CONFIG_ALTIVEC /* undef to disable */
156 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
157 CONFIG_BOOTP_BOOTFILESIZE)
159 /* Flash banks JFFS2 should use */
160 #define CFG_JFFS2_FIRST_BANK 1
161 #define CFG_JFFS2_NUM_BANKS 1
163 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
172 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
173 #include <cmd_confdefs.h>
176 * Miscellaneous configurable options
178 #define CFG_I2C_EEPROM_ADDR_LEN 1
179 #define CFG_I2C_MULTI_EEPROMS
180 #define CFG_I2C_SPEED 40000 /* I2C speed default */
182 /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
183 #define CFG_LONGHELP /* undef to save memory */
184 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
185 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
186 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
188 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
190 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
191 #define CFG_MAXARGS 16 /* max number of command args */
192 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
194 /*#define CFG_MEMTEST_START 0x00400000 memtest works on */
195 /*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
196 /*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
199 #define CFG_DRAM_TEST
201 * CFG_DRAM_TEST - enables the following tests.
203 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
204 * Environment variable 'test_dram_data' must be
206 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
207 * addressable. Environment variable
208 * 'test_dram_address' must be set to 'y'.
209 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
210 * This test takes about 6 minutes to test 64 MB.
211 * Environment variable 'test_dram_walk' must be
214 #define CFG_DRAM_TEST
215 #if defined(CFG_DRAM_TEST)
216 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
217 /* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
218 #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
219 #define CFG_DRAM_TEST_DATA
220 #define CFG_DRAM_TEST_ADDRESS
221 #define CFG_DRAM_TEST_WALK
222 #endif /* CFG_DRAM_TEST */
224 #undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
225 #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
227 #define CFG_LOAD_ADDR 0x00400000 /* default load address */
229 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
230 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
231 #define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
232 #define CFG_BUS_CLK CFG_BUS_HZ
234 #define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
235 #define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
237 /*ronen - this is the Tclk (MV64460 core) */
238 #define CFG_TCLK 133000000
241 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
243 #define CFG_750FX_HID0 0x8000c084
244 #define CFG_750FX_HID1 0x54800000
245 #define CFG_750FX_HID2 0x00000000
248 * Low Level Configuration Settings
249 * (address mappings, register initial values, etc.)
250 * You should know what you are doing if you make changes here.
253 /*-----------------------------------------------------------------------
254 * Definitions for initial stack pointer and data area
258 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
259 * To an unused memory region. The stack will remain in cache until RAM
262 #define CFG_INIT_RAM_LOCK
263 #define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
264 #define CFG_INIT_RAM_END 0x1000
265 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
266 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
268 #define RELOCATE_INTERNAL_RAM_ADDR
269 #ifdef RELOCATE_INTERNAL_RAM_ADDR
270 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
273 /*-----------------------------------------------------------------------
274 * Start addresses for the final memory configuration
275 * (Set up by the startup code)
276 * Please note that CFG_SDRAM_BASE _must_ start at 0
278 #define CFG_SDRAM_BASE 0x00000000
279 /* Dummies for BAT 4-7 */
280 #define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
281 #define CFG_SDRAM2_BASE 0x20000000
282 #define CFG_SDRAM3_BASE 0x30000000
283 #define CFG_SDRAM4_BASE 0x40000000
284 #define CFG_FLASH_BASE 0xfff00000
286 #define CFG_DFL_BOOTCS_BASE 0xff800000
287 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
289 #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
290 #define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
291 #define PCI0_IO_BASE_BOOTM 0xfd000000
293 #define CFG_RESET_ADDRESS 0xfff00100
294 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
295 #define CFG_MONITOR_BASE CFG_FLASH_BASE
296 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
298 /* areas to map different things with the GT in physical space */
299 #define CFG_DRAM_BANKS 4
301 /* What to put in the bats. */
302 #define CFG_MISC_REGION_BASE 0xf0000000
304 /* Peripheral Device section */
306 /*******************************************************/
307 /* We have on the db64460 Board : */
308 /* GT-Chipset Register Area */
309 /* GT-Chipset internal SRAM 256k */
310 /* SRAM on external device module */
311 /* Real time clock on external device module */
312 /* dobble UART on external device module */
313 /* Data flash on external device module */
314 /* Boot flash on external device module */
315 /*******************************************************/
316 #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
317 #define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
319 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
320 #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
321 #define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
323 #define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
324 #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
325 #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
326 #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
328 #define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
329 #define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
330 #define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
331 #define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
332 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
334 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
335 #define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
336 #define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
337 #define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
338 #define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
339 #define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
341 /* c 4 a 8 2 4 1 c */
342 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
343 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
344 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
345 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
348 /* ronen - update MPP Control MV64460*/
349 #define CFG_MPP_CONTROL_0 0x02222222
350 #define CFG_MPP_CONTROL_1 0x11333011
351 #define CFG_MPP_CONTROL_2 0x40431111
352 #define CFG_MPP_CONTROL_3 0x00000044
354 /*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
357 # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
358 /* gpp[31] gpp[30] gpp[29] gpp[28] */
362 /* setup new config_value for MV64460 DDR-RAM !! */
363 # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
365 #define CFG_DUART_IO CFG_DEV2_SPACE
366 #define CFG_DUART_CHAN 1 /* channel to use for console */
367 #define CFG_INIT_CHAN1
368 #define CFG_INIT_CHAN2
370 #define SRAM_BASE CFG_DEV0_SPACE
371 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
374 /*-----------------------------------------------------------------------
376 *-----------------------------------------------------------------------
379 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
380 #define PCI_HOST_FORCE 1 /* configure as pci host */
381 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
383 #define CONFIG_PCI /* include pci support */
384 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
385 #define CONFIG_PCI_PNP /* do pci plug-and-play */
386 #define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
388 /* PCI MEMORY MAP section */
389 #define CFG_PCI0_MEM_BASE 0x80000000
390 #define CFG_PCI0_MEM_SIZE _128M
391 #define CFG_PCI1_MEM_BASE 0x88000000
392 #define CFG_PCI1_MEM_SIZE _128M
394 #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
395 #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
397 /* PCI I/O MAP section */
398 #define CFG_PCI0_IO_BASE 0xfa000000
399 #define CFG_PCI0_IO_SIZE _16M
400 #define CFG_PCI1_IO_BASE 0xfb000000
401 #define CFG_PCI1_IO_SIZE _16M
403 #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
404 #define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
405 #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
406 #define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
408 #if defined (CONFIG_750CX)
409 #define CFG_PCI_IDSEL 0x0
411 #define CFG_PCI_IDSEL 0x30
413 /*----------------------------------------------------------------------
414 * Initial BAT mappings
418 * 1) GUARDED and WRITE_THRU not allowed in IBATS
419 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
423 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
424 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
425 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
426 #define CFG_DBAT0U CFG_IBAT0U
429 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
430 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
431 #define CFG_DBAT1L CFG_IBAT1L
432 #define CFG_DBAT1U CFG_IBAT1U
434 /* PCI0, PCI1 in one BAT */
435 #define CFG_IBAT2L BATL_NO_ACCESS
436 #define CFG_IBAT2U CFG_DBAT2U
437 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
438 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
440 /* GT regs, bootrom, all the devices, PCI I/O */
441 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
442 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
443 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
444 #define CFG_DBAT3U CFG_IBAT3U
446 /* I2C addresses for the two DIMM SPD chips */
447 #define DIMM0_I2C_ADDR 0x56
448 #define DIMM1_I2C_ADDR 0x54
451 * For booting Linux, the board info and command line data
452 * have to be in the first 8 MB of memory, since this is
453 * the maximum mapped by the Linux kernel during initialization.
455 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
457 /*-----------------------------------------------------------------------
460 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
461 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
463 #define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
464 #define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
465 #define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
467 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
468 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
469 #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
470 #define CFG_FLASH_CFI 1
472 #define CFG_ENV_IS_IN_FLASH 1
473 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
474 #define CFG_ENV_SECT_SIZE 0x10000
475 #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
476 /* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
478 /*-----------------------------------------------------------------------
479 * Cache Configuration
481 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
482 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
483 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
486 /*-----------------------------------------------------------------------
487 * L2CR setup -- make sure this is right for your board!
488 * look in include/mpc74xx.h for the defines used here
494 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
500 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
501 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
505 #define L2_ENABLE (L2_INIT | L2CR_L2E)
508 * Internal Definitions
512 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
513 #define BOOTFLAG_WARM 0x02 /* Software reboot */
515 #define CFG_BOARD_ASM_INIT 1
517 #endif /* __CONFIG_H */