2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
11 * 1999-nov-26: The FADS is using the following physical memorymap:
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
20 /* ------------------------------------------------------------------------- */
23 * board/config.h - configuration options, board specific
30 * High Level Configuration Options
35 #define CONFIG_FADS 1 /* old/new FADS + new ADS */
38 #define CONFIG_MPC860T 1 /* 860T */
40 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41 #undef CONFIG_8xx_CONS_SMC2
42 #undef CONFIG_8xx_CONS_NONE
43 #define CONFIG_BAUDRATE 38400
44 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
47 # define CFG_8XX_FACT 12 /* Multiply by 12 */
48 # define CFG_8XX_XIN 4000000 /* 4 MHz in */
50 # define CFG_8XX_FACT 10 /* Multiply by 10 */
51 # define CFG_8XX_XIN 5000000 /* 5 MHz in */
54 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
56 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
57 /* in general, we always know this for FADS+new ADS anyway */
58 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
61 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
63 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66 #undef CONFIG_BOOTARGS
67 #define CONFIG_BOOTCOMMAND \
69 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
70 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
73 #undef CONFIG_WATCHDOG /* watchdog disabled */
75 /* ATA / IDE and partition support */
76 #define CONFIG_MAC_PARTITION 1
77 #define CONFIG_DOS_PARTITION 1
78 #define CONFIG_ISO_PARTITION 1
80 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
81 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
82 #undef CONFIG_IDE_LED /* LED for ide not supported */
83 #undef CONFIG_IDE_RESET /* reset for ide not supported */
85 /* choose SCC1 ethernet (10BASET on motherboard)
86 * or FEC ethernet (10/100 on daughterboard)
89 #define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
90 #undef CONFIG_FEC_ENET /* disable FEC ethernet */
91 #else /* all 86x cores have FECs, if in doubt, use it */
92 #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
93 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
94 #define CFG_DISCOVER_PHY
96 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
97 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
101 #include <cmd_confdefs.h>
104 * Miscellaneous configurable options
106 #undef CFG_LONGHELP /* undef to save memory */
107 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
108 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
109 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
111 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
113 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
114 #define CFG_MAXARGS 16 /* max number of command args */
115 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
117 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
119 #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
121 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
124 #define CFG_LOAD_ADDR 0x00100000
126 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
128 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
131 * Low Level Configuration Settings
132 * (address mappings, register initial values, etc.)
133 * You should know what you are doing if you make changes here.
135 /*----------------------------------------------------------------------
136 * Internal Memory Mapped Register
138 #define CFG_IMMR 0xFF000000
139 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
141 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM)
144 #define CFG_INIT_RAM_ADDR CFG_IMMR
145 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
146 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
147 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
148 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
150 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration
152 * (Set up by the startup code)
153 * Please note that CFG_SDRAM_BASE _must_ start at 0
155 #define CFG_SDRAM_BASE 0x00000000
157 # define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */
158 #else /* !CONFIG_FADS */ /* old ADS */
159 # define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */
162 #define CFG_FLASH_BASE TEXT_BASE
164 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
166 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
167 #define CFG_MONITOR_BASE CFG_FLASH_BASE
168 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
171 * For booting Linux, the board info and command line data
172 * have to be in the first 8 MB of memory, since this is
173 * the maximum mapped by the Linux kernel during initialization.
175 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
176 /*-----------------------------------------------------------------------
179 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
180 #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
182 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
183 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
185 #define CFG_ENV_IS_IN_FLASH 1
186 #define CFG_ENV_OFFSET 0x00040000
187 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
189 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
191 /*-----------------------------------------------------------------------
192 * Cache Configuration
194 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
196 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
199 /*-----------------------------------------------------------------------
200 * SYPCR - System Protection Control 11-9
201 * SYPCR can only be written once after reset!
202 *-----------------------------------------------------------------------
203 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
205 #if defined(CONFIG_WATCHDOG)
206 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
207 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
209 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
212 /*-----------------------------------------------------------------------
213 * SIUMCR - SIU Module Configuration 11-6
214 *-----------------------------------------------------------------------
215 * PCMCIA config., multi-function pin tri-state
217 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
219 /*-----------------------------------------------------------------------
220 * TBSCR - Time Base Status and Control 11-26
221 *-----------------------------------------------------------------------
222 * Clear Reference Interrupt Status, Timebase freezing enabled
224 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
226 /*-----------------------------------------------------------------------
227 * PISCR - Periodic Interrupt Status and Control 11-31
228 *-----------------------------------------------------------------------
229 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
231 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
233 /*-----------------------------------------------------------------------
234 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
235 *-----------------------------------------------------------------------
236 * set the PLL, the low-power modes and the reset control (15-29)
238 #define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
239 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
241 /*-----------------------------------------------------------------------
242 * SCCR - System Clock and reset Control Register 15-27
243 *-----------------------------------------------------------------------
244 * Set clock output, timebase and RTC source and divider,
245 * power management and some other internal clocks
247 #define SCCR_MASK SCCR_EBDF11
248 #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
250 /*-----------------------------------------------------------------------
252 *-----------------------------------------------------------------------
257 /* Because of the way the 860 starts up and assigns CS0 the
258 * entire address space, we have to set the memory controller
259 * differently. Normally, you write the option register
260 * first, and then enable the chip select by writing the
261 * base register. For CS0, you must write the base register
262 * first, followed by the option register.
266 * Init Memory Controller:
268 * BR0/1 and OR0/1 (FLASH)
270 /* the other CS:s are determined by looking at parameters in BCSRx */
272 #define BCSR_ADDR ((uint) 0xFF010000)
273 #define BCSR_SIZE ((uint)(64 * 1024))
275 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
277 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
278 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
280 #ifdef USE_REAL_FLASH_VALUES
282 * These values fit our FADS860T ...
283 * The "default" behaviour with 1Mbyte initial doesn't work for us!
285 #define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */
286 #define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
288 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
289 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
292 /* BCSRx - Board Control and Status Registers */
293 #define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
294 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
297 * Internal Definitions
301 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
302 #define BOOTFLAG_WARM 0x02 /* Software reboot */
305 /* values according to the manual */
308 #define PCMCIA_MEM_ADDR ((uint)0xff020000)
309 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
311 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
312 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
313 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
314 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
315 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
317 /* FADS bitvalues by Helmut Buchsbaum
318 * see MPC8xxADS User's Manual for a proper description
319 * of the following structures
322 #define BCSR0_ERB ((uint)0x80000000)
323 #define BCSR0_IP ((uint)0x40000000)
324 #define BCSR0_BDIS ((uint)0x10000000)
325 #define BCSR0_BPS_MASK ((uint)0x0C000000)
326 #define BCSR0_ISB_MASK ((uint)0x01800000)
327 #define BCSR0_DBGC_MASK ((uint)0x00600000)
328 #define BCSR0_DBPC_MASK ((uint)0x00180000)
329 #define BCSR0_EBDF_MASK ((uint)0x00060000)
331 #define BCSR1_FLASH_EN ((uint)0x80000000)
332 #define BCSR1_DRAM_EN ((uint)0x40000000)
333 #define BCSR1_ETHEN ((uint)0x20000000)
334 #define BCSR1_IRDEN ((uint)0x10000000)
335 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
336 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
337 #define BCSR1_BCSR_EN ((uint)0x02000000)
338 #define BCSR1_RS232EN_1 ((uint)0x01000000)
339 #define BCSR1_PCCEN ((uint)0x00800000)
340 #define BCSR1_PCCVCC0 ((uint)0x00400000)
341 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
342 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
343 #define BCSR1_RS232EN_2 ((uint)0x00040000)
344 #define BCSR1_SDRAM_EN ((uint)0x00020000)
345 #define BCSR1_PCCVCC1 ((uint)0x00010000)
347 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
348 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
349 #define BCSR2_DRAM_PD_SHIFT (23)
350 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
351 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
353 #define BCSR3_DBID_MASK ((ushort)0x3800)
354 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
355 #define BCSR3_BREVNR0 ((ushort)0x0080)
356 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
357 #define BCSR3_BREVN1 ((ushort)0x0008)
358 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
360 #define BCSR4_ETHLOOP ((uint)0x80000000)
361 #define BCSR4_TFPLDL ((uint)0x40000000)
362 #define BCSR4_TPSQEL ((uint)0x20000000)
363 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
365 #define BCSR4_USB_EN ((uint)0x08000000)
366 #endif /* CONFIG_MPC823 */
367 #ifdef CONFIG_MPC860SAR
368 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
369 #endif /* CONFIG_MPC860SAR */
370 #ifdef CONFIG_MPC860T
371 #define BCSR4_FETH_EN ((uint)0x08000000)
372 #endif /* CONFIG_MPC860T */
374 #define BCSR4_USB_SPEED ((uint)0x04000000)
375 #endif /* CONFIG_MPC823 */
376 #ifdef CONFIG_MPC860T
377 #define BCSR4_FETHCFG0 ((uint)0x04000000)
378 #endif /* CONFIG_MPC860T */
380 #define BCSR4_VCCO ((uint)0x02000000)
381 #endif /* CONFIG_MPC823 */
382 #ifdef CONFIG_MPC860T
383 #define BCSR4_FETHFDE ((uint)0x02000000)
384 #endif /* CONFIG_MPC860T */
386 #define BCSR4_VIDEO_ON ((uint)0x00800000)
387 #endif /* CONFIG_MPC823 */
389 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
390 #endif /* CONFIG_MPC823 */
391 #ifdef CONFIG_MPC860T
392 #define BCSR4_FETHCFG1 ((uint)0x00400000)
393 #endif /* CONFIG_MPC860T */
395 #define BCSR4_VIDEO_RST ((uint)0x00200000)
396 #endif /* CONFIG_MPC823 */
397 #ifdef CONFIG_MPC860T
398 #define BCSR4_FETHRST ((uint)0x00200000)
399 #endif /* CONFIG_MPC860T */
401 #define BCSR4_MODEM_EN ((uint)0x00100000)
402 #endif /* CONFIG_MPC823 */
404 #define BCSR4_DATA_VOICE ((uint)0x00080000)
405 #endif /* CONFIG_MPC823 */
407 #define BCSR4_DATA_VOICE ((uint)0x00080000)
408 #endif /* CONFIG_MPC850 */
410 #define CONFIG_DRAM_50MHZ 1
411 #define CONFIG_SDRAM_50MHZ 1
413 /* We don't use the 8259.
415 #define NR_8259_INTS 0
419 #define _MACH_8xx (_MACH_fads)
421 #define CONFIG_DISK_SPINUP_TIME 1000000
424 /* PCMCIA configuration */
427 #define PCMCIA_SLOT_A 1
429 /*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */
430 #define CFG_PCMCIA_MEM_ADDR (0x50000000)
431 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
432 #define CFG_PCMCIA_DMA_ADDR (0x54000000)
433 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
434 #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
435 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
436 #define CFG_PCMCIA_IO_ADDR (0x5C000000)
437 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
438 /* we have 8 windows, we take everything up to 60000000 */
440 #define CFG_ATA_IDE0_OFFSET 0x0000
442 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
444 /* Offset for data I/O */
445 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
446 /* Offset for normal register accesses */
447 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
448 /* Offset for alternate registers */
449 #define CFG_ATA_ALT_OFFSET 0x0000
450 /*#define CFG_ATA_ALT_OFFSET 0x0100 */
453 #endif /* __CONFIG_H */