3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config_GEN860T.h - board specific configuration options
29 #ifndef __CONFIG_GEN860T_H
33 * High Level Configuration Options
36 #define CONFIG_GEN860T
41 #if !defined(CONFIG_SC)
42 #define CONFIG_IDENT_STRING " B2"
44 #define CONFIG_IDENT_STRING " SC"
48 * Don't depend on the RTC clock to determine clock frequency -
49 * the 860's internal rtc uses a 32.768 KHz clock which is
50 * generated by the DS1337 - and the DS1337 clock can be turned off.
52 #if !defined(CONFIG_SC)
53 #define CONFIG_8xx_GCLK_FREQ 66600000
55 #define CONFIG_8xx_GCLK_FREQ 48000000
59 * The RS-232 console port is on SMC1
61 #define CONFIG_8xx_CONS_SMC1
62 #define CONFIG_BAUDRATE 38400
65 * Set allowable console baud rates
67 #define CFG_BAUDRATE_TABLE { 9600, \
75 * Print console information
77 #undef CFG_CONSOLE_INFO_QUIET
80 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
82 #define CONFIG_BOOTDELAY 5
85 * Pass the clock frequency to the Linux kernel in units of MHz
87 #define CONFIG_CLOCKS_IN_MHZ
89 #define CONFIG_PREBOOT \
92 #undef CONFIG_BOOTARGS
93 #define CONFIG_BOOTCOMMAND \
95 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
100 * Turn off echo for serial download by default. Allow baud rate to be changed
103 #undef CONFIG_LOADS_ECHO
104 #define CFG_LOADS_BAUD_CHANGE
107 * Set default load address for tftp network downloads
109 #define CFG_TFTP_LOADADDR 0x01000000
112 * Turn off the watchdog timer
114 #undef CONFIG_WATCHDOG
117 * Do not reboot if a panic occurs
119 #define CONFIG_PANIC_HANG
122 * Enable the status LED
124 #define CONFIG_STATUS_LED
127 * Reset address. We pick an address such that when an instruction
128 * is executed at that address, a machine check exception occurs
130 #define CFG_RESET_ADDRESS ((ulong) -1)
135 #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
136 CONFIG_BOOTP_BOOTFILESIZE \
140 * The GEN860T network interface uses the on-chip 10/100 FEC with
141 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
142 * MII address is hardwired on the board to zero.
144 #define CONFIG_FEC_ENET
145 #define CFG_DISCOVER_PHY
147 #define CONFIG_PHY_ADDR 0
150 * Set default IP stuff just to get bootstrap entries into the
151 * environment so that we can autoscript the full default environment.
153 #define CONFIG_ETHADDR 9a:52:63:15:85:25
154 #define CONFIG_SERVERIP 10.0.4.201
155 #define CONFIG_IPADDR 10.0.4.111
158 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
159 * the MPC860T I2C interface.
161 #define CFG_I2C_EEPROM_ADDR 0x50
162 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
163 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
164 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
165 #define CFG_ENV_EEPROM_SIZE (32 * 1024)
168 * Enable I2C and select the hardware/software driver
170 #define CONFIG_HARD_I2C 1 /* CPM based I2C */
171 #undef CONFIG_SOFT_I2C /* Bit-banged I2C */
173 #ifdef CONFIG_HARD_I2C
174 #define CFG_I2C_SPEED 100000 /* clock speed in Hz */
175 #define CFG_I2C_SLAVE 0xFE /* I2C slave address */
178 #ifdef CONFIG_SOFT_I2C
179 #define PB_SCL 0x00000020 /* PB 26 */
180 #define PB_SDA 0x00000010 /* PB 27 */
181 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
182 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
183 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
184 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
185 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
186 else immr->im_cpm.cp_pbdat &= ~PB_SDA
187 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
188 else immr->im_cpm.cp_pbdat &= ~PB_SCL
189 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
193 * Allow environment overwrites by anyone
195 #define CONFIG_ENV_OVERWRITE
197 #if !defined(CONFIG_SC)
199 * The MPC860's internal RTC is horribly broken in rev D masks. Three
200 * internal MPC860T circuit nodes were inadvertently left floating; this
201 * causes KAPWR current in power down mode to be three orders of magnitude
202 * higher than specified in the datasheet (from 10 uA to 10 mA). No
203 * reasonable battery can keep that kind RTC running during powerdown for any
204 * length of time, so we use an external RTC on the I2C bus instead.
206 #define CONFIG_RTC_DS1337
207 #define CFG_I2C_RTC_ADDR 0x68
211 * No external RTC on SC variant, so we're stuck with the internal one.
213 #define CONFIG_RTC_MPC8xx
217 * Power On Self Test support
219 #define CONFIG_POST ( CFG_POST_CACHE | \
227 * Command line configuration.
229 #include <config_cmd_default.h>
231 #define CONFIG_CMD_ASKENV
232 #define CONFIG_CMD_DHCP
233 #define CONFIG_CMD_I2C
234 #define CONFIG_CMD_EEPROM
235 #define CONFIG_CMD_REGINFO
236 #define CONFIG_CMD_IMMAP
237 #define CONFIG_CMD_ELF
238 #define CONFIG_CMD_DATE
239 #define CONFIG_CMD_FPGA
240 #define CONFIG_CMD_MII
241 #define CONFIG_CMD_BEDBUG
243 #if !defined(CONFIG_SC)
244 #define CONFIG_CMD_DOC
248 u #define CONFIG_CMD_DIAG
252 * There is no IDE/PCMCIA hardware support on the board.
254 #undef CONFIG_IDE_PCMCIA
255 #undef CONFIG_IDE_LED
256 #undef CONFIG_IDE_RESET
259 * Enable the call to misc_init_r() for miscellaneous platform
260 * dependent initialization.
262 #define CONFIG_MISC_INIT_R
265 * Enable call to last_stage_init() so we can twiddle some LEDS :)
267 #define CONFIG_LAST_STAGE_INIT
270 * Virtex2 FPGA configuration support
272 #define CONFIG_FPGA_COUNT 1
273 #define CONFIG_FPGA CFG_XILINX_VIRTEX2
274 #define CFG_FPGA_PROG_FEEDBACK
277 #define CFG_NAND_LEGACY
280 * Verbose help from command monitor.
283 #if !defined(CONFIG_SC)
284 #define CFG_PROMPT "B2> "
286 #define CFG_PROMPT "SC> "
291 * Use the "hush" command parser
293 #define CFG_HUSH_PARSER
294 #define CFG_PROMPT_HUSH_PS2 "> "
297 * Set buffer size for console I/O
299 #if defined(CONFIG_CMD_KGDB)
300 #define CFG_CBSIZE 1024
302 #define CFG_CBSIZE 256
308 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
311 * Maximum number of arguments that a command can accept
313 #define CFG_MAXARGS 16
316 * Boot argument buffer size
318 #define CFG_BARGSIZE CFG_CBSIZE
321 * Default memory test range
323 #define CFG_MEMTEST_START 0x0100000
324 #define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
327 * Select the more full-featured memory test
329 #define CFG_ALT_MEMTEST
332 * Default load address
334 #define CFG_LOAD_ADDR 0x01000000
337 * Set decrementer frequency (1 ms ticks)
342 * Device memory map (after SDRAM remap to 0x0):
344 * CS Device Base Addr Size
345 * ----------------------------------------------------
346 * CS0* Flash 0x40000000 64 M
347 * CS1* SDRAM 0x00000000 16 M
348 * CS2* Disk-On-Chip 0x50000000 32 K
349 * CS3* FPGA 0x60000000 64 M
350 * CS4* SelectMap 0x70000000 32 K
351 * CS5* Mil-Std 1553 I/F 0x80000000 32 K
354 * IMMR 860T Registers 0xfff00000
358 * Base addresses and block sizes
360 #define CFG_IMMR 0xFF000000
362 #define SDRAM_BASE 0x00000000
363 #define SDRAM_SIZE (64 * 1024 * 1024)
365 #define FLASH_BASE 0x40000000
366 #define FLASH_SIZE (16 * 1024 * 1024)
368 #define DOC_BASE 0x50000000
369 #define DOC_SIZE (32 * 1024)
371 #define FPGA_BASE 0x60000000
372 #define FPGA_SIZE (64 * 1024 * 1024)
374 #define SELECTMAP_BASE 0x70000000
375 #define SELECTMAP_SIZE (32 * 1024)
377 #define M1553_BASE 0x80000000
378 #define M1553_SIZE (64 * 1024)
381 * Definitions for initial stack pointer and data area (in DPRAM)
383 #define CFG_INIT_RAM_ADDR CFG_IMMR
384 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
385 #define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
386 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
387 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
390 * Start addresses for the final memory configuration
391 * (Set up by the startup code)
392 * Please note that CFG_SDRAM_BASE _must_ start at 0
394 #define CFG_SDRAM_BASE SDRAM_BASE
399 #define CFG_FLASH_BASE FLASH_BASE
400 #define CFG_FLASH_SIZE FLASH_SIZE
401 #define CFG_FLASH_SECT_SIZE (128 * 1024)
402 #define CFG_MAX_FLASH_BANKS 1
403 #define CFG_MAX_FLASH_SECT 128
406 * The timeout values are for an entire chip and are in milliseconds.
407 * Yes I know that the write timeout is huge. Accroding to the
408 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
409 * case VCC and temp after 100K programming cycles. It works out
410 * to 280 minutes (might as well be forever).
412 #define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
413 #define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
416 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
418 #define CFG_DIRECT_FLASH_TFTP
421 * Reserve memory for U-Boot.
423 #define CFG_MAX_UBOOT_SECTS 4
424 #define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
425 #define CFG_MONITOR_BASE CFG_FLASH_BASE
428 * Select environment placement. NOTE that u-boot.lds must
429 * be edited if this is changed!
431 #undef CFG_ENV_IS_IN_FLASH
432 #define CFG_ENV_IS_IN_EEPROM
434 #if defined(CFG_ENV_IS_IN_EEPROM)
435 #define CFG_ENV_SIZE (2 * 1024)
436 #define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
438 #define CFG_ENV_SIZE 0x1000
439 #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
442 * This ultimately gets passed right into the linker script, so we have to
445 #define CFG_ENV_OFFSET 0x060000
449 * Reserve memory for malloc()
451 #define CFG_MALLOC_LEN (128 * 1024)
454 * For booting Linux, the board info and command line data
455 * have to be in the first 8 MB of memory, since this is
456 * the maximum mapped by the Linux kernel during initialization.
458 #define CFG_BOOTMAPSZ (8 * 1024 * 1024)
461 * Cache Configuration
463 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
464 #if defined(CONFIG_CMD_KGDB)
465 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
468 /*------------------------------------------------------------------------
469 * SYPCR - System Protection Control UM 11-9
470 * -----------------------------------------------------------------------
471 * SYPCR can only be written once after reset!
473 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
475 #if defined(CONFIG_WATCHDOG)
476 #define CFG_SYPCR ( SYPCR_SWTC | \
485 #define CFG_SYPCR ( SYPCR_SWTC | \
493 /*-----------------------------------------------------------------------
494 * SIUMCR - SIU Module Configuration UM 11-6
495 *-----------------------------------------------------------------------
496 * Set debug pin mux, enable SPKROUT and GPLB5*.
498 #define CFG_SIUMCR ( SIUMCR_DBGC11 | \
504 /*-----------------------------------------------------------------------
505 * TBSCR - Time Base Status and Control UM 11-26
506 *-----------------------------------------------------------------------
507 * Clear Reference Interrupt Status, Timebase freeze enabled
509 #define CFG_TBSCR ( TBSCR_REFA | \
514 /*-----------------------------------------------------------------------
515 * RTCSC - Real-Time Clock Status and Control Register UM 11-27
516 *-----------------------------------------------------------------------
518 #define CFG_RTCSC ( RTCSC_SEC | \
524 /*-----------------------------------------------------------------------
525 * PISCR - Periodic Interrupt Status and Control UM 11-31
526 *-----------------------------------------------------------------------
527 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
529 #define CFG_PISCR ( PISCR_PS | \
533 /*-----------------------------------------------------------------------
534 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
535 *-----------------------------------------------------------------------
536 * Reset PLL lock status sticky bit, timer expired status bit and timer
537 * interrupt status bit. Set MF for 1:2:1 mode.
539 #define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
545 /*-----------------------------------------------------------------------
546 * SCCR - System Clock and reset Control Register UM 15-27
547 *-----------------------------------------------------------------------
548 * Set clock output, timebase and RTC source and divider,
549 * power management and some other internal clocks
551 #define SCCR_MASK SCCR_EBDF11
553 #if !defined(CONFIG_SC)
554 #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
555 SCCR_COM00 | /* full strength CLKOUT */ \
556 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
557 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
562 #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
563 SCCR_COM00 | /* full strength CLKOUT */ \
564 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
565 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
573 /*-----------------------------------------------------------------------
574 * DER - Debug Enable Register UM 37-46
575 *-----------------------------------------------------------------------
576 * Mask all events that can cause entry into debug mode
581 * Initialize Memory Controller:
583 * BR0 and OR0 (FLASH memory)
585 #define FLASH_BASE0_PRELIM FLASH_BASE
590 #define CFG_PRELIM_OR_AM 0xfe000000
594 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
596 #define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
604 #define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
605 CFG_OR_TIMING_FLASH \
608 #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
615 * SDRAM configuration
617 #define CFG_OR1_AM 0xfc000000
618 #define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
622 #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
629 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
632 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
635 * Periodic timer for refresh @ 33 MHz system clock
637 #define CFG_MAMR_PTA 64
640 * MAMR settings for SDRAM
642 #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
653 * CS2* configuration for Disk On Chip:
654 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
657 #define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
666 #define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
673 * CS3* configuration for FPGA:
674 * 33 MHz bus with SCY=15, no burst.
675 * The FPGA uses TA and TEA to terminate bus cycles, but we
676 * clear SETA and set the cycle length to a large number so that
677 * the cycle will still complete even if there is a configuration
678 * error that prevents TA from asserting on FPGA accesss.
680 #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
685 #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
691 * CS4* configuration for FPGA SelectMap configuration interface.
692 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
695 #define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
700 #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
707 * CS5* configuration for Mil-Std 1553 databus interface.
708 * 33 MHz bus, GPCM, no burst.
709 * The 1553 interface uses TA and TEA to terminate bus cycles,
710 * but we clear SETA and set the cycle length to a large number so that
711 * the cycle will still complete even if there is a configuration
712 * error that prevents TA from asserting on FPGA accesss.
714 #define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
722 #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
731 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
732 #define BOOTFLAG_WARM 0x02 /* Software reboot */
735 * Disk On Chip (millenium) configuration
737 #if !defined(CONFIG_SC)
738 #define CFG_MAX_DOC_DEVICE 1
739 #undef CFG_DOC_SUPPORT_2000
740 #define CFG_DOC_SUPPORT_MILLENNIUM
741 #undef CFG_DOC_PASSIVE_PROBE
745 * FEC interrupt assignment
747 #define FEC_INTERRUPT SIU_LEVEL1
752 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
753 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
756 #endif /* __CONFIG_GEN860T_H */
758 /* vim: set ts=4 tw=78 ai shiftwidth=4: */