3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC8272_FAMILY 1
21 #define CONFIG_IDS8247 1
22 #define CPU_ID_STR "MPC8247"
23 #define CONFIG_CPM2 1 /* Has a CPM2 */
25 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
29 #define CONFIG_BOOTCOUNT_LIMIT
31 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
33 #undef CONFIG_BOOTARGS
35 #define CONFIG_EXTRA_ENV_SETTINGS \
37 "nfsargs=setenv bootargs root=/dev/nfs rw " \
38 "nfsroot=${serverip}:${rootpath}\0" \
39 "ramargs=setenv bootargs root=/dev/ram rw " \
40 "console=ttyS0,115200\0" \
41 "addip=setenv bootargs ${bootargs} " \
42 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
43 ":${hostname}:${netdev}:off panic=1\0" \
44 "flash_nfs=run nfsargs addip;" \
45 "bootm ${kernel_addr}\0" \
46 "flash_self=run ramargs addip;" \
47 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
48 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
49 "rootpath=/opt/eldk/ppc_82xx\0" \
50 "bootfile=/tftpboot/IDS8247/uImage\0" \
51 "kernel_addr=ff800000\0" \
52 "ramdisk_addr=ffa00000\0" \
54 #define CONFIG_BOOTCOMMAND "run flash_self"
56 #define CONFIG_MISC_INIT_R 1
58 /* enable I2C and select the hardware/software driver */
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
61 #define CONFIG_SYS_I2C_SOFT_SPEED 400000
62 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
64 * Software (bit-bang) I2C driver configuration
67 #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
68 #define I2C_ACTIVE (iop->pdir |= 0x00000080)
69 #define I2C_TRISTATE (iop->pdir &= ~0x00000080)
70 #define I2C_READ ((iop->pdat & 0x00000080) != 0)
71 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
72 else iop->pdat &= ~0x00000080
73 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
74 else iop->pdat &= ~0x00000100
75 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
78 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
79 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
80 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
81 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
87 * select serial console configuration
88 * use the extern UART for the console
90 #define CONFIG_CONS_INDEX 1
91 #define CONFIG_BAUDRATE 115200
93 * NS16550 Configuration
95 #define CONFIG_SYS_NS16550
96 #define CONFIG_SYS_NS16550_SERIAL
98 #define CONFIG_SYS_NS16550_REG_SIZE 1
100 #define CONFIG_SYS_NS16550_CLK 14745600
102 #define CONFIG_SYS_UART_BASE 0xE0000000
103 #define CONFIG_SYS_UART_SIZE 0x10000
105 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
108 /* pass open firmware flat tree */
109 #define CONFIG_OF_LIBFDT 1
110 #define CONFIG_OF_BOARD_SETUP 1
112 #define OF_TBCLK (bd->bi_busfreq / 4)
113 #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
117 * select ethernet configuration
119 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
120 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
123 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
124 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
126 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
127 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
128 #undef CONFIG_ETHER_NONE /* define if ether on something else */
129 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
130 #define CONFIG_ETHER_ON_FCC1
136 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
137 * - Enable Full Duplex in FSMR
139 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
140 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
141 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
142 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
145 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
146 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
148 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
149 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
151 #undef CONFIG_WATCHDOG /* watchdog disabled */
153 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
158 #define CONFIG_BOOTP_SUBNETMASK
159 #define CONFIG_BOOTP_GATEWAY
160 #define CONFIG_BOOTP_HOSTNAME
161 #define CONFIG_BOOTP_BOOTPATH
162 #define CONFIG_BOOTP_BOOTFILESIZE
164 #define CONFIG_RTC_PCF8563
165 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
168 * Command line configuration.
170 #include <config_cmd_default.h>
172 #define CONFIG_CMD_DHCP
173 #define CONFIG_CMD_NFS
174 #define CONFIG_CMD_NAND
175 #define CONFIG_CMD_I2C
176 #define CONFIG_CMD_SNTP
180 * Miscellaneous configurable options
182 #define CONFIG_SYS_LONGHELP /* undef to save memory */
183 #if defined(CONFIG_CMD_KGDB)
184 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
186 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
189 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
190 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
192 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
193 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
195 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
197 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
204 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
206 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
207 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
208 #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
209 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
210 /* What should the base address of the main FLASH be and how big is
211 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
212 * The main FLASH is whichever is connected to *CS0.
214 #define CONFIG_SYS_FLASH0_BASE 0xFFF00000
215 #define CONFIG_SYS_FLASH0_SIZE 8
217 /* Flash bank size (for preliminary settings)
219 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
221 /*-----------------------------------------------------------------------
224 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
226 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
227 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
229 /* Environment in flash */
230 #define CONFIG_ENV_IS_IN_FLASH 1
231 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
232 #define CONFIG_ENV_SIZE 0x20000
233 #define CONFIG_ENV_SECT_SIZE 0x20000
235 /*-----------------------------------------------------------------------
237 *-----------------------------------------------------------------------
239 #if defined(CONFIG_CMD_NAND)
241 #define CONFIG_SYS_NAND0_BASE 0xE1000000
242 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
244 #endif /* CONFIG_CMD_NAND */
246 /*-----------------------------------------------------------------------
247 * Hard Reset Configuration Words
249 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
250 * defines for the various registers affected by the HRCW e.g. changing
251 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
253 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
255 /* no slaves so just fill with zeros */
256 #define CONFIG_SYS_HRCW_SLAVE1 0
257 #define CONFIG_SYS_HRCW_SLAVE2 0
258 #define CONFIG_SYS_HRCW_SLAVE3 0
259 #define CONFIG_SYS_HRCW_SLAVE4 0
260 #define CONFIG_SYS_HRCW_SLAVE5 0
261 #define CONFIG_SYS_HRCW_SLAVE6 0
262 #define CONFIG_SYS_HRCW_SLAVE7 0
264 /*-----------------------------------------------------------------------
265 * Internal Memory Mapped Register
267 #define CONFIG_SYS_IMMR 0xF0000000
269 /*-----------------------------------------------------------------------
270 * Definitions for initial stack pointer and data area (in DPRAM)
272 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
273 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
277 /*-----------------------------------------------------------------------
278 * Start addresses for the final memory configuration
279 * (Set up by the startup code)
280 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
282 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
284 #define CONFIG_SYS_SDRAM_BASE 0x00000000
285 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
286 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
287 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
288 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
290 /*-----------------------------------------------------------------------
291 * Cache Configuration
293 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
294 #if defined(CONFIG_CMD_KGDB)
295 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
298 /*-----------------------------------------------------------------------
299 * HIDx - Hardware Implementation-dependent Registers 2-11
300 *-----------------------------------------------------------------------
301 * HID0 also contains cache control - initially enable both caches and
302 * invalidate contents, then the final state leaves only the instruction
303 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
304 * but Soft reset does not.
306 * HID1 has only read-only information - nothing to set.
309 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
310 #define CONFIG_SYS_HID0_FINAL 0
311 #define CONFIG_SYS_HID2 0
313 /*-----------------------------------------------------------------------
314 * RMR - Reset Mode Register 5-5
315 *-----------------------------------------------------------------------
316 * turn on Checkstop Reset Enable
318 #define CONFIG_SYS_RMR 0
320 /*-----------------------------------------------------------------------
321 * BCR - Bus Configuration 4-25
322 *-----------------------------------------------------------------------
324 #define CONFIG_SYS_BCR 0
326 /*-----------------------------------------------------------------------
327 * SIUMCR - SIU Module Configuration 4-31
328 *-----------------------------------------------------------------------
330 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
332 /*-----------------------------------------------------------------------
333 * SYPCR - System Protection Control 4-35
334 * SYPCR can only be written once after reset!
335 *-----------------------------------------------------------------------
336 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
338 #if defined(CONFIG_WATCHDOG)
339 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
340 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
342 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
343 SYPCR_SWRI|SYPCR_SWP)
344 #endif /* CONFIG_WATCHDOG */
346 /*-----------------------------------------------------------------------
347 * TMCNTSC - Time Counter Status and Control 4-40
348 *-----------------------------------------------------------------------
349 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
350 * and enable Time Counter
352 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
354 /*-----------------------------------------------------------------------
355 * PISCR - Periodic Interrupt Status and Control 4-42
356 *-----------------------------------------------------------------------
357 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
360 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
362 /*-----------------------------------------------------------------------
363 * SCCR - System Clock Control 9-8
364 *-----------------------------------------------------------------------
365 * Ensure DFBRG is Divide by 16
367 #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
369 /*-----------------------------------------------------------------------
370 * RCCR - RISC Controller Configuration 13-7
371 *-----------------------------------------------------------------------
373 #define CONFIG_SYS_RCCR 0
376 * Init Memory Controller:
378 * Bank Bus Machine PortSz Device
379 * ---- --- ------- ------ ------
380 * 0 60x GPCM 16 bit FLASH
381 * 1 60x GPCM 8 bit NAND
382 * 2 60x SDRAM 32 bit SDRAM
383 * 3 60x GPCM 8 bit UART
387 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
389 /* Minimum mask to separate preliminary
390 * address ranges for CS[0:2]
392 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
394 #define CONFIG_SYS_MPTPR 0x6600
396 /*-----------------------------------------------------------------------------
397 * Address for Mode Register Set (MRS) command
398 *-----------------------------------------------------------------------------
400 #define CONFIG_SYS_MRS_OFFS 0x00000110
405 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
410 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
413 #if defined(CONFIG_CMD_NAND)
414 /* Bank 1 - NAND Flash
416 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
417 #define CONFIG_SYS_NAND_SIZE 0x8000
419 #define CONFIG_SYS_OR_TIMING_NAND 0x000036
421 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
422 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
425 /* Bank 2 - 60x bus SDRAM
427 #define CONFIG_SYS_PSRT 0x20
428 #define CONFIG_SYS_LSRT 0x20
430 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
435 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
438 /* SDRAM initialization values
440 #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
442 ORxS_ROWST_PBI0_A9 |\
445 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
446 PSDMR_BSMA_A15_A17 |\
447 PSDMR_SDA10_PBI0_A10 |\
459 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
460 #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
462 #endif /* __CONFIG_H */