2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
34 * High Level Configuration Options
38 #define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
39 #define CONFIG_KUP4X 1 /* ...on a KUP4X module */
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate */
46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53 #define CONFIG_BOARD_TYPES 1 /* support board types */
55 #define CFG_8XX_FACT 8 /* Multiply by 8 */
56 #define CFG_8XX_XIN 16000000 /* 16 MHz in */
59 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
61 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
62 /* in general, we always know this for FADS+new ADS anyway */
63 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
66 #undef CONFIG_BOOTARGS
69 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
71 "run addhw;diskboot 200000 0:1;bootm 200000\0" \
72 "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
73 "run addhw;diskboot 200000 2:1;bootm 200000\0" \
74 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
75 "panic_boot=echo No Bootdevice !!! reset\0" \
76 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
77 "ramargs=setenv bootargs root=/dev/ram rw\0" \
78 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
79 ":$(netmask):$(hostname):$(netdev):off\0" \
80 "addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
83 "load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
84 "update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
85 "cp.b 200000 40040000 14000\0"
87 #define CONFIG_BOOTCOMMAND \
88 "run slot_a_boot;run nfs_boot;run panic_boot"
91 #define CONFIG_MISC_INIT_R 1
92 #define CONFIG_MISC_INIT_F 1
94 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
97 #undef CONFIG_WATCHDOG /* watchdog disabled */
99 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
101 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
103 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
105 #define CONFIG_MAC_PARTITION
106 #define CONFIG_DOS_PARTITION
108 #define CONFIG_HARD_I2C
109 #define CFG_I2C_SPEED 40000
110 #define CFG_I2C_SLAVE 0x7F
112 #define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
113 #undef CONFIG_KUP4K_LOGO
115 /* Define to allow the user to overwrite serial and ethaddr */
116 #define CONFIG_ENV_OVERWRITE
118 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
125 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
126 #include <cmd_confdefs.h>
129 * Miscellaneous configurable options
131 #define CFG_LONGHELP /* undef to save memory */
132 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
133 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
134 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
136 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
138 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
139 #define CFG_MAXARGS 16 /* max number of command args */
140 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
142 #define CFG_MEMTEST_START 0x000400000 /* memtest works on */
143 #define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
144 #define CFG_LOAD_ADDR 0x200000 /* default load address */
146 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
148 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
150 #define CFG_CONSOLE_INFO_QUIET 1
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
157 /*-----------------------------------------------------------------------
158 * Internal Memory Mapped Register
160 #define CFG_IMMR 0xFFF00000
162 /*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM)
165 #define CFG_INIT_RAM_ADDR CFG_IMMR
166 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
167 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
168 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
169 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
171 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CFG_SDRAM_BASE _must_ start at 0
176 #define CFG_SDRAM_BASE 0x00000000
177 #define CFG_FLASH_BASE 0x40000000
178 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
179 #define CFG_MONITOR_BASE CFG_FLASH_BASE
180 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
187 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 /*-----------------------------------------------------------------------
192 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193 #define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
195 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
196 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
198 #define CFG_ENV_IS_IN_FLASH 1
199 #define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
200 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
201 #define CFG_ENV_SECT_SIZE 0x10000
203 /* Address and size of Redundant Environment Sector */
205 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
206 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
208 /*-----------------------------------------------------------------------
209 * Hardware Information Block
212 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
213 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
214 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
216 /*-----------------------------------------------------------------------
217 * Cache Configuration
219 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
220 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
221 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
224 /*-----------------------------------------------------------------------
225 * SYPCR - System Protection Control 11-9
226 * SYPCR can only be written once after reset!
227 *-----------------------------------------------------------------------
228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
230 #if defined(CONFIG_WATCHDOG)
231 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
234 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
237 /*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
242 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
244 /*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
249 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
252 /*-----------------------------------------------------------------------
253 * PISCR - Periodic Interrupt Status and Control 11-31
254 *-----------------------------------------------------------------------
255 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
257 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
260 /*-----------------------------------------------------------------------
261 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262 *-----------------------------------------------------------------------
263 * set the PLL, the low-power modes and the reset control (15-29)
265 #define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \
266 PLPRCR_SPLSS | PLPRCR_TEXPS)
269 /*-----------------------------------------------------------------------
270 * SCCR - System Clock and reset Control Register 15-27
271 *-----------------------------------------------------------------------
272 * Set clock output, timebase and RTC source and divider,
273 * power management and some other internal clocks
275 #define SCCR_MASK SCCR_EBDF00
276 #define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \
277 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
278 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
281 /*-----------------------------------------------------------------------
283 *-----------------------------------------------------------------------
287 /* KUP4K use both slots, SLOT_A as "primary". */
288 #define CONFIG_PCMCIA_SLOT_A 1
290 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
291 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
292 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
293 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
294 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
295 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
297 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
299 #define PCMCIA_SOCKETS_NO 1
300 #define PCMCIA_MEM_WIN_NO 8
301 /*-----------------------------------------------------------------------
302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303 *-----------------------------------------------------------------------
306 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
308 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
309 #define CONFIG_IDE_LED 1 /* LED for ide supported */
310 #undef CONFIG_IDE_RESET /* reset for ide not supported */
312 #define CFG_IDE_MAXBUS 1
313 #define CFG_IDE_MAXDEVICE 2
315 #define CFG_ATA_IDE0_OFFSET 0x0000
317 #define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
319 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
321 /* Offset for data I/O */
322 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
324 /* Offset for normal register accesses */
325 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
327 /* Offset for alternate registers */
328 #define CFG_ATA_ALT_OFFSET 0x0100
331 /*-----------------------------------------------------------------------
333 *-----------------------------------------------------------------------
339 * Init Memory Controller:
341 * BR0/1 and OR0/1 (FLASH)
343 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
345 /* used to re-map FLASH both when starting from SRAM or FLASH:
346 * restrict access enough to keep SRAM working (if any)
347 * but not too much to meddle with FLASH accesses
349 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
350 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
355 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
356 OR_SCY_2_CLK | OR_EHTR | OR_BI)
358 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
359 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
360 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
363 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
364 #define CFG_OR_TIMING_SDRAM 0x00000A00
367 #define CFG_MPTPR 0x400
370 * MAMR settings for SDRAM
372 #define CFG_MAMR 0x80802114
376 * Internal Definitions
380 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
381 #define BOOTFLAG_WARM 0x02 /* Software reboot */
384 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
386 #define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
388 #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
389 #define CONFIG_SILENT_CONSOLE 1
391 #define CONFIG_USB_STORAGE 1
392 #define CONFIG_USB_SL811HS 1
394 #endif /* __CONFIG_H */