2 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
31 #define CONFIG_BOOTP_BOOTFILESIZE
36 # define CONFIG_MII_INIT 1
37 # define CONFIG_SYS_DISCOVER_PHY
38 # define CONFIG_SYS_RX_ETH_BUFFER 8
39 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
41 # define CONFIG_SYS_FEC0_PINMUX 0
42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
43 # define MCFFEC_TOUT_LOOP 50000
44 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
45 # ifndef CONFIG_SYS_DISCOVER_PHY
46 # define FECDUPLEX FULL
47 # define FECSPEED _100BASET
49 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
52 # endif /* CONFIG_SYS_DISCOVER_PHY */
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_i2C_FSL
62 #define CONFIG_SYS_FSL_I2C_SPEED 80000
63 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
64 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
65 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
66 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
67 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
68 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
70 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
71 #define CONFIG_BOOTFILE "u-boot.bin"
73 # define CONFIG_IPADDR 192.162.1.2
74 # define CONFIG_NETMASK 255.255.255.0
75 # define CONFIG_SERVERIP 192.162.1.1
76 # define CONFIG_GATEWAYIP 192.162.1.1
79 #define CONFIG_HOSTNAME "M5235EVB"
80 #define CONFIG_EXTRA_ENV_SETTINGS \
83 "u-boot=u-boot.bin\0" \
84 "load=tftp ${loadaddr) ${u-boot}\0" \
85 "upd=run load; run prog\0" \
86 "prog=prot off ffe00000 ffe3ffff;" \
87 "era ffe00000 ffe3ffff;" \
88 "cp.b ${loadaddr} ffe00000 ${filesize};"\
92 #define CONFIG_PRAM 512 /* 512 KB */
94 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
96 #define CONFIG_SYS_CLK 75000000
97 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
99 #define CONFIG_SYS_MBAR 0x40000000
102 * Low Level Configuration Settings
103 * (address mappings, register initial values, etc.)
104 * You should know what you are doing if you make changes here.
106 /*-----------------------------------------------------------------------
107 * Definitions for initial stack pointer and data area (in DPRAM)
109 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
110 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
111 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
112 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
115 /*-----------------------------------------------------------------------
116 * Start addresses for the final memory configuration
117 * (Set up by the startup code)
118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
120 #define CONFIG_SYS_SDRAM_BASE 0x00000000
121 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
123 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
124 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
126 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
127 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
129 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
130 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
133 * For booting Linux, the board info and command line data
134 * have to be in the first 8 MB of memory, since this is
135 * the maximum mapped by the Linux kernel during initialization ??
137 /* Initial Memory map for Linux */
138 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
139 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
141 /*-----------------------------------------------------------------------
144 #define CONFIG_SYS_FLASH_CFI
145 #ifdef CONFIG_SYS_FLASH_CFI
146 # define CONFIG_FLASH_CFI_DRIVER 1
147 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
148 #ifdef NORFLASH_PS32BIT
149 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
151 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
153 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
154 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
155 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
158 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
160 /* Configuration for environment
161 * Environment is embedded in u-boot in the second sector of the flash
164 #define LDS_BOARD_TEXT \
165 . = DEFINED(env_offset) ? env_offset : .; \
166 env/embedded.o(.text);
168 #ifdef NORFLASH_PS32BIT
169 # define CONFIG_ENV_OFFSET (0x8000)
170 # define CONFIG_ENV_SIZE 0x4000
171 # define CONFIG_ENV_SECT_SIZE 0x4000
173 # define CONFIG_ENV_OFFSET (0x4000)
174 # define CONFIG_ENV_SIZE 0x2000
175 # define CONFIG_ENV_SECT_SIZE 0x2000
178 /*-----------------------------------------------------------------------
179 * Cache Configuration
181 #define CONFIG_SYS_CACHELINE_SIZE 16
183 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
184 CONFIG_SYS_INIT_RAM_SIZE - 8)
185 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
186 CONFIG_SYS_INIT_RAM_SIZE - 4)
187 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
188 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
189 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
190 CF_ACR_EN | CF_ACR_SM_ALL)
191 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
192 CF_CACR_CEIB | CF_CACR_DCM | \
195 /*-----------------------------------------------------------------------
196 * Chipselect bank definitions
199 * CS0 - NOR Flash 1, 2, 4, or 8MB
208 #ifdef NORFLASH_PS32BIT
209 # define CONFIG_SYS_CS0_BASE 0xFFC00000
210 # define CONFIG_SYS_CS0_MASK 0x003f0001
211 # define CONFIG_SYS_CS0_CTRL 0x00001D00
213 # define CONFIG_SYS_CS0_BASE 0xFFE00000
214 # define CONFIG_SYS_CS0_MASK 0x001f0001
215 # define CONFIG_SYS_CS0_CTRL 0x00001D80
218 #endif /* _M5329EVB_H */