2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_M5253EVBE /* define board type */
15 #define CONFIG_MCFUART
16 #define CONFIG_SYS_UART_PORT (0)
18 #undef CONFIG_WATCHDOG /* disable watchdog */
21 /* Configuration for environment
22 * Environment is embedded in u-boot in the second sector of the flash
24 #ifndef CONFIG_MONITOR_IS_IN_RAM
25 #define CONFIG_ENV_OFFSET 0x4000
26 #define CONFIG_ENV_SECT_SIZE 0x2000
28 #define CONFIG_ENV_ADDR 0xffe04000
29 #define CONFIG_ENV_SECT_SIZE 0x2000
32 #define LDS_BOARD_TEXT \
33 . = DEFINED(env_offset) ? env_offset : .; \
39 #undef CONFIG_BOOTP_BOOTFILESIZE
40 #undef CONFIG_BOOTP_BOOTPATH
41 #undef CONFIG_BOOTP_GATEWAY
42 #undef CONFIG_BOOTP_HOSTNAME
45 * Command line configuration.
49 #define CONFIG_IDE_RESET 1
50 #define CONFIG_IDE_PREINIT 1
54 #define CONFIG_SYS_IDE_MAXBUS 1
55 #define CONFIG_SYS_IDE_MAXDEVICE 2
57 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
58 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
60 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
61 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
62 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
63 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
65 #define CONFIG_SYS_LONGHELP /* undef to save memory */
67 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
68 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
69 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
71 #define CONFIG_SYS_LOAD_ADDR 0x00100000
73 #define CONFIG_SYS_MEMTEST_START 0x400
74 #define CONFIG_SYS_MEMTEST_END 0x380000
76 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
77 #define CONFIG_SYS_FAST_CLK
78 #ifdef CONFIG_SYS_FAST_CLK
79 # define CONFIG_SYS_PLLCR 0x1243E054
80 # define CONFIG_SYS_CLK 140000000
82 # define CONFIG_SYS_PLLCR 0x135a4140
83 # define CONFIG_SYS_CLK 70000000
87 * Low Level Configuration Settings
88 * (address mappings, register initial values, etc.)
89 * You should know what you are doing if you make changes here.
92 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
93 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
96 * Definitions for initial stack pointer and data area (in DPRAM)
98 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
99 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
104 * Start addresses for the final memory configuration
105 * (Set up by the startup code)
106 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
108 #define CONFIG_SYS_SDRAM_BASE 0x00000000
109 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
111 #ifdef CONFIG_MONITOR_IS_IN_RAM
112 #define CONFIG_SYS_MONITOR_BASE 0x20000
114 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
117 #define CONFIG_SYS_MONITOR_LEN 0x40000
118 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
119 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
122 * For booting Linux, the board info and command line data
123 * have to be in the first 8 MB of memory, since this is
124 * the maximum mapped by the Linux kernel during initialization ??
126 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
127 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
129 /* FLASH organization */
130 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
133 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
135 #define CONFIG_SYS_FLASH_CFI 1
136 #define CONFIG_FLASH_CFI_DRIVER 1
137 #define CONFIG_SYS_FLASH_SIZE 0x200000
138 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
140 /* Cache Configuration */
141 #define CONFIG_SYS_CACHELINE_SIZE 16
143 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
144 CONFIG_SYS_INIT_RAM_SIZE - 8)
145 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
146 CONFIG_SYS_INIT_RAM_SIZE - 4)
147 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
148 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
150 CF_ACR_EN | CF_ACR_SM_ALL)
151 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
152 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
153 CF_ACR_EN | CF_ACR_SM_ALL)
154 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
157 /* Port configuration */
158 #define CONFIG_SYS_FECI2C 0xF0
160 #define CONFIG_SYS_CS0_BASE 0xFFE00000
161 #define CONFIG_SYS_CS0_MASK 0x001F0021
162 #define CONFIG_SYS_CS0_CTRL 0x00001D80
164 /*-----------------------------------------------------------------------
167 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
168 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
169 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
170 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
171 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
172 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
173 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
175 #endif /* _M5253EVB_H */