2 * Configuation settings for the Freescale MCF53017EVB.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 5000
29 /* Command line configuration */
30 #include <config_cmd_default.h>
32 #define CONFIG_CMD_CACHE
33 #define CONFIG_CMD_DATE
34 #define CONFIG_CMD_ELF
35 #define CONFIG_CMD_FLASH
37 #define CONFIG_CMD_MEMORY
38 #define CONFIG_CMD_MISC
39 #define CONFIG_CMD_MII
40 #define CONFIG_CMD_PING
41 #define CONFIG_CMD_REGINFO
43 #define CONFIG_SYS_UNIFY_CACHE
48 # define CONFIG_MII_INIT 1
49 # define CONFIG_SYS_DISCOVER_PHY
50 # define CONFIG_SYS_RX_ETH_BUFFER 8
51 # define CONFIG_SYS_TX_ETH_BUFFER 8
52 # define CONFIG_SYS_FEC_BUF_USE_SRAM
53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
54 # define CONFIG_HAS_ETH1
56 # define CONFIG_SYS_FEC0_PINMUX 0
57 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
58 # define CONFIG_SYS_FEC1_PINMUX 0
59 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
60 # define MCFFEC_TOUT_LOOP 50000
62 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
65 # ifndef CONFIG_SYS_DISCOVER_PHY
66 # define FECDUPLEX FULL
67 # define FECSPEED _100BASET
69 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
70 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
72 # endif /* CONFIG_SYS_DISCOVER_PHY */
77 #define CONFIG_SYS_RTC_CNT (0x8000)
78 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
85 #define CONFIG_SYS_I2C
86 #define CONFIG_SYS_I2C_FSL
87 #define CONFIG_SYS_FSL_I2C_SPEED 80000
88 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
89 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
90 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
92 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
93 #define CONFIG_UDP_CHECKSUM
96 # define CONFIG_IPADDR 192.162.1.2
97 # define CONFIG_NETMASK 255.255.255.0
98 # define CONFIG_SERVERIP 192.162.1.1
99 # define CONFIG_GATEWAYIP 192.162.1.1
100 #endif /* FEC_ENET */
102 #define CONFIG_HOSTNAME M53017
103 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "loadaddr=40010000\0" \
106 "u-boot=u-boot.bin\0" \
107 "load=tftp ${loadaddr) ${u-boot}\0" \
108 "upd=run load; run prog\0" \
109 "prog=prot off 0 3ffff;" \
111 "cp.b ${loadaddr} 0 ${filesize};" \
115 #define CONFIG_PRAM 512 /* 512 KB */
116 #define CONFIG_SYS_PROMPT "-> "
117 #define CONFIG_SYS_LONGHELP /* undef to save memory */
119 #ifdef CONFIG_CMD_KGDB
120 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
122 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
126 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
128 #define CONFIG_SYS_LOAD_ADDR 0x40010000
130 #define CONFIG_SYS_CLK 80000000
131 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
133 #define CONFIG_SYS_MBAR 0xFC000000
136 * Low Level Configuration Settings
137 * (address mappings, register initial values, etc.)
138 * You should know what you are doing if you make changes here.
141 * Definitions for initial stack pointer and data area (in DPRAM)
143 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
144 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
145 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
146 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
150 * Start addresses for the final memory configuration
151 * (Set up by the startup code)
152 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
154 #define CONFIG_SYS_SDRAM_BASE 0x40000000
155 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
156 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
157 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
158 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
159 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
160 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
162 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
163 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
165 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
166 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
168 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
169 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization ??
176 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
177 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
179 /*-----------------------------------------------------------------------
182 #define CONFIG_SYS_FLASH_CFI
183 #ifdef CONFIG_SYS_FLASH_CFI
184 # define CONFIG_FLASH_CFI_DRIVER 1
185 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
186 # define CONFIG_FLASH_SPANSION_S29WS_N 1
187 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
188 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
189 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
190 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
191 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
194 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
196 /* Configuration for environment
197 * Environment is embedded in u-boot in the second sector of the flash
199 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
200 #define CONFIG_ENV_SIZE 0x1000
201 #define CONFIG_ENV_SECT_SIZE 0x8000
202 #define CONFIG_ENV_IS_IN_FLASH 1
204 #define LDS_BOARD_TEXT \
205 . = DEFINED(env_offset) ? env_offset : .; \
206 common/env_embedded.o (.text*)
208 /*-----------------------------------------------------------------------
209 * Cache Configuration
211 #define CONFIG_SYS_CACHELINE_SIZE 16
213 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
214 CONFIG_SYS_INIT_RAM_SIZE - 8)
215 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
216 CONFIG_SYS_INIT_RAM_SIZE - 4)
217 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
218 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
219 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
220 CF_ACR_EN | CF_ACR_SM_ALL)
221 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
224 /*-----------------------------------------------------------------------
225 * Chipselect bank definitions
235 #define CONFIG_SYS_CS0_BASE 0
236 #define CONFIG_SYS_CS0_MASK 0x00FF0001
237 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
239 #define CONFIG_SYS_CS1_BASE 0xC0000000
240 #define CONFIG_SYS_CS1_MASK 0x00070001
241 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
243 #endif /* _M53017EVB_H */