2 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_MCF532x /* define processor family */
38 #define CONFIG_M5329 /* define processor type */
42 #define CONFIG_MCFUART
43 #define CFG_UART_PORT (0)
44 #define CONFIG_BAUDRATE 115200
45 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
47 #undef CONFIG_WATCHDOG
48 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
50 #define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \
56 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
66 # define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND)
68 # define CONFIG_COMMANDS (DEFAULT_COMMANDS)
71 #define CFG_UNIFY_CACHE
75 # define CONFIG_NET_MULTI 1
77 # define CFG_DISCOVER_PHY
78 # define CFG_RX_ETH_BUFFER 8
79 # define CFG_FAULT_ECHO_LINK_DOWN
81 # define CFG_FEC0_PINMUX 0
82 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
83 # define MCFFEC_TOUT_LOOP 50000
84 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
85 # ifndef CFG_DISCOVER_PHY
86 # define FECDUPLEX FULL
87 # define FECSPEED _100BASET
89 # ifndef CFG_FAULT_ECHO_LINK_DOWN
90 # define CFG_FAULT_ECHO_LINK_DOWN
92 # endif /* CFG_DISCOVER_PHY */
103 #define CONFIG_FSL_I2C
104 #define CONFIG_HARD_I2C /* I2C with hw support */
105 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
106 #define CFG_I2C_SPEED 80000
107 #define CFG_I2C_SLAVE 0x7F
108 #define CFG_I2C_OFFSET 0x58000
109 #define CFG_IMMR CFG_MBAR
111 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
112 #include <cmd_confdefs.h>
113 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
115 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
116 # define CONFIG_IPADDR 192.162.1.2
117 # define CONFIG_NETMASK 255.255.255.0
118 # define CONFIG_SERVERIP 192.162.1.1
119 # define CONFIG_GATEWAYIP 192.162.1.1
120 # define CONFIG_OVERWRITE_ETHADDR_ONCE
121 #endif /* FEC_ENET */
123 #define CONFIG_HOSTNAME M5329EVB
124 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "loadaddr=40010000\0" \
127 "u-boot=u-boot.bin\0" \
128 "load=tftp ${loadaddr) ${u-boot}\0" \
129 "upd=run load; run prog\0" \
130 "prog=prot off 0 2ffff;" \
132 "cp.b ${loadaddr} 0 ${filesize};" \
136 #define CONFIG_PRAM 512 /* 512 KB */
137 #define CFG_PROMPT "-> "
138 #define CFG_LONGHELP /* undef to save memory */
140 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
141 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
143 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
146 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
147 #define CFG_MAXARGS 16 /* max number of command args */
148 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
149 #define CFG_LOAD_ADDR 0x40010000
152 #define CFG_CLK 80000000
153 #define CFG_CPU_CLK CFG_CLK * 3
155 #define CFG_MBAR 0xFC000000
157 #define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
160 * Low Level Configuration Settings
161 * (address mappings, register initial values, etc.)
162 * You should know what you are doing if you make changes here.
164 /*-----------------------------------------------------------------------
165 * Definitions for initial stack pointer and data area (in DPRAM)
167 #define CFG_INIT_RAM_ADDR 0x80000000
168 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
169 #define CFG_INIT_RAM_CTRL 0x221
170 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
171 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
172 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
174 /*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
177 * Please note that CFG_SDRAM_BASE _must_ start at 0
179 #define CFG_SDRAM_BASE 0x40000000
180 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
181 #define CFG_SDRAM_CFG1 0x53722730
182 #define CFG_SDRAM_CFG2 0x56670000
183 #define CFG_SDRAM_CTRL 0xE1092000
184 #define CFG_SDRAM_EMOD 0x40010000
185 #define CFG_SDRAM_MODE 0x018D0000
187 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
188 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
190 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
191 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
193 #define CFG_BOOTPARAMS_LEN 64*1024
194 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization ??
201 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203 /*-----------------------------------------------------------------------
206 #define CFG_FLASH_CFI
208 # define CFG_FLASH_CFI_DRIVER 1
209 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
210 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
211 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
212 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
213 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
216 #ifdef NANDFLASH_SIZE
217 # define CFG_MAX_NAND_DEVICE 1
218 # define CFG_NAND_BASE (CFG_CS2_BASE << 16)
219 # define CFG_NAND_SIZE 1
220 # define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
221 # define NAND_MAX_CHIPS 1
222 # define NAND_ALLOW_ERASE_ALL 1
223 # define CONFIG_JFFS2_NAND 1
224 # define CONFIG_JFFS2_DEV "nand0"
225 # define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
226 # define CONFIG_JFFS2_PART_OFFSET 0x00000000
229 #define CFG_FLASH_BASE 0
230 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
232 /* Configuration for environment
233 * Environment is embedded in u-boot in the second sector of the flash
235 #define CFG_ENV_OFFSET 0x4000
236 #define CFG_ENV_SECT_SIZE 0x2000
237 #define CFG_ENV_IS_IN_FLASH 1
238 #define CFG_ENV_IS_EMBEDDED 1
240 /*-----------------------------------------------------------------------
241 * Cache Configuration
243 #define CFG_CACHELINE_SIZE 16
245 /*-----------------------------------------------------------------------
246 * Chipselect bank definitions
249 * CS0 - NOR Flash 1, 2, 4, or 8MB
250 * CS1 - CompactFlash and registers
251 * CS2 - NAND Flash 16, 32, or 64MB
256 #define CFG_CS0_BASE 0
257 #define CFG_CS0_MASK 0x007f0001
258 #define CFG_CS0_CTRL 0x00001fa0
260 #define CFG_CS1_BASE 0x1000
261 #define CFG_CS1_MASK 0x001f0001
262 #define CFG_CS1_CTRL 0x002A3780
264 #ifdef NANDFLASH_SIZE
265 #define CFG_CS2_BASE 0x2000
266 #define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
267 #define CFG_CS2_CTRL 0x00001f60
270 #define CONFIG_UDP_CHECKSUM
272 #endif /* _M5329EVB_H */