2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54418TWR /* M54418TWR board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
27 #undef CONFIG_WATCHDOG
29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
34 #define CONFIG_BOOTP_BOOTFILESIZE
35 #define CONFIG_BOOTP_BOOTPATH
36 #define CONFIG_BOOTP_GATEWAY
37 #define CONFIG_BOOTP_HOSTNAME
42 #ifdef CONFIG_CMD_NAND
43 #define CONFIG_JFFS2_NAND
44 #define CONFIG_NAND_FSL_NFC
45 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
46 #define CONFIG_SYS_MAX_NAND_DEVICE 1
47 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
48 #define CONFIG_SYS_NAND_SELECT_DEVICE
51 /* Network configuration */
55 #define CONFIG_MII_INIT 1
56 #define CONFIG_SYS_DISCOVER_PHY
57 #define CONFIG_SYS_RX_ETH_BUFFER 2
58 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
59 #define CONFIG_SYS_TX_ETH_BUFFER 2
60 #define CONFIG_HAS_ETH1
62 #define CONFIG_SYS_FEC0_PINMUX 0
63 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
64 #define CONFIG_SYS_FEC1_PINMUX 0
65 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
66 #define MCFFEC_TOUT_LOOP 50000
67 #define CONFIG_SYS_FEC0_PHYADDR 0
68 #define CONFIG_SYS_FEC1_PHYADDR 1
71 #ifdef CONFIG_SYS_NAND_BOOT
72 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
73 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
74 "-(jffs2) console=ttyS0,115200"
76 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
77 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
78 __stringify(CONFIG_IPADDR) " ip=" \
79 __stringify(CONFIG_IPADDR) ":" \
80 __stringify(CONFIG_SERVERIP)":" \
81 __stringify(CONFIG_GATEWAYIP)": " \
82 __stringify(CONFIG_NETMASK) \
83 "::eth0:off:rw console=ttyS0,115200"
86 #define CONFIG_ETHPRIME "FEC0"
87 #define CONFIG_IPADDR 192.168.1.2
88 #define CONFIG_NETMASK 255.255.255.0
89 #define CONFIG_SERVERIP 192.168.1.1
90 #define CONFIG_GATEWAYIP 192.168.1.1
92 #define CONFIG_SYS_FEC_BUF_USE_SRAM
93 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
94 #ifndef CONFIG_SYS_DISCOVER_PHY
95 #define FECDUPLEX FULL
96 #define FECSPEED _100BASET
100 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
101 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
103 #endif /* CONFIG_SYS_DISCOVER_PHY */
106 #define CONFIG_HOSTNAME M54418TWR
108 #if defined(CONFIG_CF_SBF)
109 /* ST Micro serial flash */
110 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
111 #define CONFIG_EXTRA_ENV_SETTINGS \
113 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
114 "loadaddr=0x40010000\0" \
115 "sbfhdr=sbfhdr.bin\0" \
116 "uboot=u-boot.bin\0" \
117 "load=tftp ${loadaddr} ${sbfhdr};" \
118 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
119 "upd=run load; run prog\0" \
120 "prog=sf probe 0:1 1000000 3;" \
121 "sf erase 0 40000;" \
122 "sf write ${loadaddr} 0 40000;" \
125 #elif defined(CONFIG_SYS_NAND_BOOT)
126 #define CONFIG_EXTRA_ENV_SETTINGS \
128 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
129 "loadaddr=0x40010000\0" \
130 "u-boot=u-boot.bin\0" \
131 "load=tftp ${loadaddr} ${u-boot};\0" \
132 "upd=run load; run prog\0" \
133 "prog=nand device 0;" \
134 "nand erase 0 40000;" \
135 "nb_update ${loadaddr} ${filesize};" \
139 #define CONFIG_SYS_UBOOT_END 0x3FFFF
140 #define CONFIG_EXTRA_ENV_SETTINGS \
142 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
143 "loadaddr=40010000\0" \
144 "u-boot=u-boot.bin\0" \
145 "load=tftp ${loadaddr) ${u-boot}\0" \
146 "upd=run load; run prog\0" \
147 "prog=prot off mram" " ;" \
148 "cp.b ${loadaddr} 0 ${filesize};" \
155 #define CONFIG_RTC_MCFRRTC
156 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
159 #define CONFIG_MCFTMR
163 #undef CONFIG_SYS_FSL_I2C
164 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
165 /* I2C speed and slave address */
166 #define CONFIG_SYS_I2C_SPEED 80000
167 #define CONFIG_SYS_I2C_SLAVE 0x7F
168 #define CONFIG_SYS_I2C_OFFSET 0x58000
169 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
171 /* DSPI and Serial Flash */
172 #define CONFIG_CF_SPI
173 #define CONFIG_CF_DSPI
174 #define CONFIG_SERIAL_FLASH
175 #define CONFIG_HARD_SPI
176 #define CONFIG_SYS_SBFHDR_SIZE 0x7
177 #ifdef CONFIG_CMD_SPI
179 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
180 DSPI_CTAR_PCSSCK_1CLK | \
181 DSPI_CTAR_PASC(0) | \
183 DSPI_CTAR_CSSCK(0) | \
186 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
187 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
190 /* Input, PCI, Flexbus, and VCO */
191 #define CONFIG_EXTRA_CLOCK
193 #define CONFIG_PRAM 2048 /* 2048 KB */
195 #define CONFIG_SYS_LONGHELP /* undef to save memory */
197 #if defined(CONFIG_CMD_KGDB)
198 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
200 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
202 /* Print Buffer Size */
203 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
204 sizeof(CONFIG_SYS_PROMPT) + 16)
205 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
206 /* Boot Argument Buffer Size */
207 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
209 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
211 #define CONFIG_SYS_MBAR 0xFC000000
214 * Low Level Configuration Settings
215 * (address mappings, register initial values, etc.)
216 * You should know what you are doing if you make changes here.
219 /*-----------------------------------------------------------------------
220 * Definitions for initial stack pointer and data area (in DPRAM)
222 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
223 /* End of used area in internal SRAM */
224 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
225 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
226 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
227 GENERATED_GBL_DATA_SIZE) - 32)
228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
229 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
231 /*-----------------------------------------------------------------------
232 * Start addresses for the final memory configuration
233 * (Set up by the startup code)
234 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
236 #define CONFIG_SYS_SDRAM_BASE 0x40000000
237 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
239 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
240 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
241 #define CONFIG_SYS_DRAM_TEST
243 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
244 #define CONFIG_SERIAL_BOOT
247 #if defined(CONFIG_SERIAL_BOOT)
248 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
250 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
253 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
254 /* Reserve 256 kB for Monitor */
255 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
256 /* Reserve 256 kB for malloc() */
257 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
260 * For booting Linux, the board info and command line data
261 * have to be in the first 8 MB of memory, since this is
262 * the maximum mapped by the Linux kernel during initialization ??
264 /* Initial Memory map for Linux */
265 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
266 (CONFIG_SYS_SDRAM_SIZE << 20))
268 /* Configuration for environment
269 * Environment is embedded in u-boot in the second sector of the flash
271 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
272 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
273 #define CONFIG_ENV_SIZE 0x1000
276 #if defined(CONFIG_CF_SBF)
277 #define CONFIG_ENV_SPI_CS 1
278 #define CONFIG_ENV_OFFSET 0x40000
279 #define CONFIG_ENV_SIZE 0x2000
280 #define CONFIG_ENV_SECT_SIZE 0x10000
282 #if defined(CONFIG_SYS_NAND_BOOT)
283 #define CONFIG_ENV_OFFSET 0x80000
284 #define CONFIG_ENV_SIZE 0x20000
285 #define CONFIG_ENV_SECT_SIZE 0x20000
287 #undef CONFIG_ENV_OVERWRITE
289 /* FLASH organization */
290 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
292 #undef CONFIG_SYS_FLASH_CFI
293 #ifdef CONFIG_SYS_FLASH_CFI
295 #define CONFIG_FLASH_CFI_DRIVER 1
296 /* Max size that the board might have */
297 #define CONFIG_SYS_FLASH_SIZE 0x1000000
298 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
299 /* max number of memory banks */
300 #define CONFIG_SYS_MAX_FLASH_BANKS 1
301 /* max number of sectors on one chip */
302 #define CONFIG_SYS_MAX_FLASH_SECT 270
303 /* "Real" (hardware) sectors protection */
304 #define CONFIG_SYS_FLASH_PROTECTION
305 #define CONFIG_SYS_FLASH_CHECKSUM
306 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
308 /* max number of sectors on one chip */
309 #define CONFIG_SYS_MAX_FLASH_SECT 270
310 /* max number of sectors on one chip */
311 #define CONFIG_SYS_MAX_FLASH_BANKS 0
315 * This is setting for JFFS2 support in u-boot.
316 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
318 #ifdef CONFIG_CMD_JFFS2
319 #define CONFIG_JFFS2_DEV "nand0"
320 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
321 #define CONFIG_MTD_DEVICE
322 #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
324 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
330 #ifdef CONFIG_CMD_UBI
331 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
332 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
333 #define MTDIDS_DEFAULT "nand0=NAND"
334 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
337 /* Cache Configuration */
338 #define CONFIG_SYS_CACHELINE_SIZE 16
339 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
340 CONFIG_SYS_INIT_RAM_SIZE - 8)
341 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
342 CONFIG_SYS_INIT_RAM_SIZE - 4)
343 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
344 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
345 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
346 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
347 CF_ACR_EN | CF_ACR_SM_ALL)
348 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
349 CF_CACR_ICINVA | CF_CACR_EUSP)
350 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
351 CF_CACR_DEC | CF_CACR_DDCM_P | \
352 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
354 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
355 CONFIG_SYS_INIT_RAM_SIZE - 12)
357 /*-----------------------------------------------------------------------
358 * Memory bank definitions
361 * CS0 - NOR Flash 16MB
370 #define CONFIG_SYS_CS0_BASE 0x00000000
371 #define CONFIG_SYS_CS0_MASK 0x000F0101
372 #define CONFIG_SYS_CS0_CTRL 0x00001D60
374 #endif /* _M54418TWR_H */