2 * Configuation settings for the Freescale MCF54451 EVB board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54451EVB /* M54451EVB board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
26 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
28 #undef CONFIG_WATCHDOG
30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 #define CONFIG_BOOTP_BOOTFILESIZE
36 #define CONFIG_BOOTP_BOOTPATH
37 #define CONFIG_BOOTP_GATEWAY
38 #define CONFIG_BOOTP_HOSTNAME
40 /* Network configuration */
44 # define CONFIG_MII_INIT 1
45 # define CONFIG_SYS_DISCOVER_PHY
46 # define CONFIG_SYS_RX_ETH_BUFFER 8
47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
49 # define CONFIG_SYS_FEC0_PINMUX 0
50 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
51 # define MCFFEC_TOUT_LOOP 50000
53 # define CONFIG_ETHPRIME "FEC0"
54 # define CONFIG_IPADDR 192.162.1.2
55 # define CONFIG_NETMASK 255.255.255.0
56 # define CONFIG_SERVERIP 192.162.1.1
57 # define CONFIG_GATEWAYIP 192.162.1.1
59 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
60 # ifndef CONFIG_SYS_DISCOVER_PHY
61 # define FECDUPLEX FULL
62 # define FECSPEED _100BASET
64 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
65 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
67 # endif /* CONFIG_SYS_DISCOVER_PHY */
70 #define CONFIG_HOSTNAME M54451EVB
71 #ifdef CONFIG_SYS_STMICRO_BOOT
72 /* ST Micro serial flash */
73 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
74 #define CONFIG_EXTRA_ENV_SETTINGS \
76 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
77 "loadaddr=0x40010000\0" \
78 "sbfhdr=sbfhdr.bin\0" \
79 "uboot=u-boot.bin\0" \
80 "load=tftp ${loadaddr} ${sbfhdr};" \
81 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
82 "upd=run load; run prog\0" \
83 "prog=sf probe 0:1 1000000 3;" \
85 "sf write ${loadaddr} 0 30000;" \
89 #define CONFIG_SYS_UBOOT_END 0x3FFFF
90 #define CONFIG_EXTRA_ENV_SETTINGS \
92 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
93 "loadaddr=40010000\0" \
94 "u-boot=u-boot.bin\0" \
95 "load=tftp ${loadaddr) ${u-boot}\0" \
96 "upd=run load; run prog\0" \
97 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
98 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
99 "cp.b ${loadaddr} 0 ${filesize};" \
105 #define CONFIG_MCFRTC
107 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
110 #define CONFIG_MCFTMR
114 #define CONFIG_SYS_I2C
115 #define CONFIG_SYS_I2C_FSL
116 #define CONFIG_SYS_FSL_I2C_SPEED 80000
117 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
118 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
119 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
121 /* DSPI and Serial Flash */
122 #define CONFIG_CF_SPI
123 #define CONFIG_CF_DSPI
124 #define CONFIG_SERIAL_FLASH
125 #define CONFIG_HARD_SPI
126 #define CONFIG_SYS_SBFHDR_SIZE 0x7
127 #ifdef CONFIG_CMD_SPI
129 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
130 DSPI_CTAR_PCSSCK_1CLK | \
131 DSPI_CTAR_PASC(0) | \
133 DSPI_CTAR_CSSCK(0) | \
136 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
137 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
140 /* Input, PCI, Flexbus, and VCO */
141 #define CONFIG_EXTRA_CLOCK
143 #define CONFIG_PRAM 2048 /* 2048 KB */
145 #define CONFIG_SYS_LONGHELP /* undef to save memory */
147 #if defined(CONFIG_CMD_KGDB)
148 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
150 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
152 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
153 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
154 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
156 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
158 #define CONFIG_SYS_MBAR 0xFC000000
161 * Low Level Configuration Settings
162 * (address mappings, register initial values, etc.)
163 * You should know what you are doing if you make changes here.
166 /*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
169 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
171 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
172 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
174 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
176 /*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
181 #define CONFIG_SYS_SDRAM_BASE 0x40000000
182 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
183 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
184 #define CONFIG_SYS_SDRAM_CFG2 0x57670000
185 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
186 #define CONFIG_SYS_SDRAM_EMOD 0x80810000
187 #define CONFIG_SYS_SDRAM_MODE 0x008D0000
188 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
190 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
191 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
194 # define CONFIG_SERIAL_BOOT
195 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
197 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
199 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
200 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
202 /* Reserve 256 kB for malloc() */
203 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
205 * For booting Linux, the board info and command line data
206 * have to be in the first 8 MB of memory, since this is
207 * the maximum mapped by the Linux kernel during initialization ??
209 /* Initial Memory map for Linux */
210 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
212 /* Configuration for environment
213 * Environment is not embedded in u-boot. First time runing may have env
214 * crc error warning if there is no correct environment on the flash.
216 #if defined(CONFIG_SYS_STMICRO_BOOT)
217 # define CONFIG_ENV_SPI_CS 1
218 # define CONFIG_ENV_OFFSET 0x20000
219 # define CONFIG_ENV_SIZE 0x2000
220 # define CONFIG_ENV_SECT_SIZE 0x10000
222 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
223 # define CONFIG_ENV_SIZE 0x2000
224 # define CONFIG_ENV_SECT_SIZE 0x20000
226 #undef CONFIG_ENV_OVERWRITE
228 /* FLASH organization */
229 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
231 #define CONFIG_SYS_FLASH_CFI
232 #ifdef CONFIG_SYS_FLASH_CFI
234 # define CONFIG_FLASH_CFI_DRIVER 1
235 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
236 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
237 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
238 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
239 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
240 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
241 # define CONFIG_SYS_FLASH_CHECKSUM
242 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
247 * This is setting for JFFS2 support in u-boot.
248 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
250 #ifdef CONFIG_CMD_JFFS2
251 # define CONFIG_JFFS2_DEV "nor0"
252 # define CONFIG_JFFS2_PART_SIZE 0x01000000
253 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
256 /* Cache Configuration */
257 #define CONFIG_SYS_CACHELINE_SIZE 16
259 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
260 CONFIG_SYS_INIT_RAM_SIZE - 8)
261 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
262 CONFIG_SYS_INIT_RAM_SIZE - 4)
263 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
264 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
265 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
266 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
267 CF_ACR_EN | CF_ACR_SM_ALL)
268 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
269 CF_CACR_ICINVA | CF_CACR_EUSP)
270 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
271 CF_CACR_DEC | CF_CACR_DDCM_P | \
272 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
274 /*-----------------------------------------------------------------------
275 * Memory bank definitions
278 * CS0 - NOR Flash 16MB
287 #define CONFIG_SYS_CS0_BASE 0x00000000
288 #define CONFIG_SYS_CS0_MASK 0x00FF0001
289 #define CONFIG_SYS_CS0_CTRL 0x00004D80
291 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
293 #endif /* _M54451EVB_H */