2 * Configuation settings for the Freescale MCF5485 FireEngine board.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
37 #define CONFIG_MCF547x_8x /* define processor family */
38 #define CONFIG_M548x /* define processor type */
39 #define CONFIG_M5485 /* define processor type */
41 #define CONFIG_MCFUART
42 #define CFG_UART_PORT (0)
43 #define CONFIG_BAUDRATE 115200
44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
46 #define CONFIG_HW_WATCHDOG
47 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
49 /* Command line configuration */
50 #include <config_cmd_default.h>
52 #define CONFIG_CMD_CACHE
53 #undef CONFIG_CMD_DATE
54 #define CONFIG_CMD_ELF
55 #define CONFIG_CMD_FLASH
56 #define CONFIG_CMD_I2C
57 #define CONFIG_CMD_MEMORY
58 #define CONFIG_CMD_MISC
59 #define CONFIG_CMD_MII
60 #define CONFIG_CMD_NET
61 #define CONFIG_CMD_PCI
62 #define CONFIG_CMD_PING
63 #define CONFIG_CMD_REGINFO
64 #define CONFIG_CMD_USB
68 #define CONFIG_FSLDMAFEC
69 #ifdef CONFIG_FSLDMAFEC
70 # define CONFIG_NET_MULTI 1
72 # define CONFIG_HAS_ETH1
74 # define CFG_DISCOVER_PHY
75 # define CFG_RX_ETH_BUFFER 32
76 # define CFG_TX_ETH_BUFFER 48
77 # define CFG_FAULT_ECHO_LINK_DOWN
79 # define CFG_FEC0_PINMUX 0
80 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
81 # define CFG_FEC1_PINMUX 0
82 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
84 # define MCFFEC_TOUT_LOOP 50000
85 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
86 # ifndef CFG_DISCOVER_PHY
87 # define FECDUPLEX FULL
88 # define FECSPEED _100BASET
90 # ifndef CFG_FAULT_ECHO_LINK_DOWN
91 # define CFG_FAULT_ECHO_LINK_DOWN
93 # endif /* CFG_DISCOVER_PHY */
95 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
96 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
97 # define CONFIG_IPADDR 192.162.1.2
98 # define CONFIG_NETMASK 255.255.255.0
99 # define CONFIG_SERVERIP 192.162.1.1
100 # define CONFIG_GATEWAYIP 192.162.1.1
101 # define CONFIG_OVERWRITE_ETHADDR_ONCE
105 #ifdef CONFIG_CMD_USB
106 # define CONFIG_USB_STORAGE
107 # define CONFIG_DOS_PARTITION
108 # define CONFIG_USB_OHCI_NEW
109 # ifndef CONFIG_CMD_PCI
110 # define CONFIG_CMD_PCI
112 /*# define CONFIG_PCI_OHCI*/
113 # define CFG_USB_OHCI_REGS_BASE 0x80041000
114 # define CFG_USB_OHCI_MAX_ROOT_PORTS 15
115 # define CFG_USB_OHCI_SLOT_NAME "isp1561"
116 # define CFG_OHCI_SWAP_REG_ACCESS
120 #define CONFIG_FSL_I2C
121 #define CONFIG_HARD_I2C /* I2C with hw support */
122 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
123 #define CFG_I2C_SPEED 80000
124 #define CFG_I2C_SLAVE 0x7F
125 #define CFG_I2C_OFFSET 0x00008F00
126 #define CFG_IMMR CFG_MBAR
129 #ifdef CONFIG_CMD_PCI
131 #define CONFIG_PCI_PNP 1
132 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
134 #define CFG_PCI_MEM_BUS 0x80000000
135 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
136 #define CFG_PCI_MEM_SIZE 0x10000000
138 #define CFG_PCI_IO_BUS 0x71000000
139 #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
140 #define CFG_PCI_IO_SIZE 0x01000000
142 #define CFG_PCI_CFG_BUS 0x70000000
143 #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
144 #define CFG_PCI_CFG_SIZE 0x01000000
147 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
148 #define CONFIG_UDP_CHECKSUM
150 #define CONFIG_HOSTNAME M548xEVB
151 #define CONFIG_EXTRA_ENV_SETTINGS \
154 "u-boot=u-boot.bin\0" \
155 "load=tftp ${loadaddr) ${u-boot}\0" \
156 "upd=run load; run prog\0" \
157 "prog=prot off bank 1;" \
158 "era ff800000 ff82ffff;" \
159 "cp.b ${loadaddr} ff800000 ${filesize};"\
163 #define CONFIG_PRAM 512 /* 512 KB */
164 #define CFG_PROMPT "-> "
165 #define CFG_LONGHELP /* undef to save memory */
167 #ifdef CONFIG_CMD_KGDB
168 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
170 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
173 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
174 #define CFG_MAXARGS 16 /* max number of command args */
175 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
176 #define CFG_LOAD_ADDR 0x00010000
179 #define CFG_CLK CFG_BUSCLK
180 #define CFG_CPU_CLK CFG_CLK * 2
182 #define CFG_MBAR 0xF0000000
183 #define CFG_INTSRAM (CFG_MBAR + 0x10000)
184 #define CFG_INTSRAMSZ 0x8000
186 /*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
189 * Low Level Configuration Settings
190 * (address mappings, register initial values, etc.)
191 * You should know what you are doing if you make changes here.
193 /*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
196 #define CFG_INIT_RAM_ADDR 0xF2000000
197 #define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
198 #define CFG_INIT_RAM_CTRL 0x21
199 #define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
200 #define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
201 #define CFG_INIT_RAM1_CTRL 0x21
202 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
203 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
204 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
206 /*-----------------------------------------------------------------------
207 * Start addresses for the final memory configuration
208 * (Set up by the startup code)
209 * Please note that CFG_SDRAM_BASE _must_ start at 0
211 #define CFG_SDRAM_BASE 0x00000000
212 #define CFG_SDRAM_CFG1 0x73711630
213 #define CFG_SDRAM_CFG2 0x46370000
214 #define CFG_SDRAM_CTRL 0xE10B0000
215 #define CFG_SDRAM_EMOD 0x40010000
216 #define CFG_SDRAM_MODE 0x018D0000
217 #define CFG_SDRAM_DRVSTRENGTH 0x000002AA
219 # define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
221 # define CFG_SDRAM_SIZE CFG_DRAMSZ
224 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
225 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
227 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
228 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
230 #define CFG_BOOTPARAMS_LEN 64*1024
231 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization ??
238 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
240 /*-----------------------------------------------------------------------
243 #define CFG_FLASH_CFI
245 # define CFG_FLASH_BASE (CFG_CS0_BASE)
246 # define CFG_FLASH_CFI_DRIVER 1
247 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
248 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
249 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
250 # define CFG_FLASH_USE_BUFFER_WRITE
252 # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
253 # define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
254 # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
256 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
257 # define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
261 /* Configuration for environment
262 * Environment is embedded in u-boot in the second sector of the flash
264 #define CFG_ENV_OFFSET 0x2000
265 #define CFG_ENV_SECT_SIZE 0x2000
266 #define CFG_ENV_IS_IN_FLASH 1
267 #define CFG_ENV_IS_EMBEDDED 1
269 /*-----------------------------------------------------------------------
270 * Cache Configuration
272 #define CFG_CACHELINE_SIZE 16
274 /*-----------------------------------------------------------------------
275 * Chipselect bank definitions
278 * CS0 - NOR Flash 1, 2, 4, or 8MB
285 #define CFG_CS0_BASE 0xFF800000
286 #define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
287 #define CFG_CS0_CTRL 0x00101980
290 #define CFG_CS1_BASE 0xF8000000
291 #define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
292 #define CFG_CS1_CTRL 0x00000D80
295 #endif /* _M5485EVB_H */