3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
37 * High Level Configuration Options
41 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
42 #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */
44 #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
46 /* allow serial and ethaddr to be overwritten */
47 #define CONFIG_ENV_OVERWRITE
50 * select serial console configuration
52 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
53 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
56 * if CONFIG_CONS_NONE is defined, then the serial console routines must
57 * defined elsewhere (for example, on the cogent platform, there are serial
58 * ports on the motherboard which are used for the serial console - see
59 * cogent/cma101/serial.[ch]).
61 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
62 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
63 #undef CONFIG_CONS_NONE /* define if console on something else */
64 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
67 * select ethernet configuration
69 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
70 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
73 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
74 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
75 * from CONFIG_COMMANDS to remove support for networking.
77 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
78 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
79 #undef CONFIG_ETHER_NONE /* define if ether on something else */
80 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
82 #if (CONFIG_ETHER_INDEX == 2)
87 * - Select bus for bd/buffers (see 28-13)
90 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
91 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
92 # define CFG_CPMFCR_RAMTYPE 0
93 # define CFG_FCC_PSMR 0
95 #endif /* CONFIG_ETHER_INDEX */
98 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
99 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
100 #define CFG_I2C_SLAVE 0x7F
101 #define CFG_I2C_EEPROM_ADDR_LEN 1
103 /*-----------------------------------------------------------------------
104 * Definitions for Serial Presence Detect EEPROM address
105 * (to get SDRAM settings)
107 #define SPD_EEPROM_ADDRESS 0x50
110 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
111 #define CONFIG_BAUDRATE 115200
114 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
138 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139 #include <cmd_confdefs.h>
142 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
144 #define CONFIG_BOOTARGS "root=/dev/ram rw"
146 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
148 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
149 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
150 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
151 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
154 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
157 * Miscellaneous configurable options
159 #define CFG_LONGHELP /* undef to save memory */
160 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
161 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
162 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
164 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
166 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
167 #define CFG_MAXARGS 16 /* max number of command args */
168 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
170 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
171 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
173 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
174 /* for versions < 2.4.5-pre5 */
176 #define CFG_LOAD_ADDR 0x100000 /* default load address */
178 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
180 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
182 #define CFG_FLASH_BASE 0xff800000
183 #define FLASH_BASE 0xff800000
184 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
185 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
186 #define CFG_FLASH_SIZE 8
187 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
188 #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
190 #undef CFG_FLASH_CHECKSUM
192 /* this is stuff came out of the Motorola docs */
193 /* Only change this if you also change the Hardware configuration Word */
194 #define CFG_DEFAULT_IMMR 0x0F010000
197 #define CFG_IMMR 0x04700000
198 #define CFG_BCSR 0x04500000
201 /* Set IMMR to 0xF0000000 or above to boot Linux */
202 #define CFG_IMMR 0xF0000000
203 #define CFG_BCSR 0x04500000
205 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
207 /*#define CONFIG_VERY_BIG_RAM 1*/
209 /* What should be the base address of SDRAM DIMM and how big is
210 * it (in Mbytes)? This will normally auto-configure via the SPD.
212 #define CFG_SDRAM_BASE 0x00000000
213 #define CFG_SDRAM_SIZE 16
215 #define SDRAM_SPD_ADDR 0x50
218 /*-----------------------------------------------------------------------
219 * BR2,BR3 - Base Register
220 * Ref: Section 10.3.1 on page 10-14
221 * OR2,OR3 - Option Register
222 * Ref: Section 10.3.2 on page 10-16
223 *-----------------------------------------------------------------------
226 /* Bank 2,3 - SDRAM DIMM
229 /* The BR2 is configured as follows:
231 * - Base address of 0x00000000
232 * - 64 bit port size (60x bus only)
233 * - Data errors checking is disabled
234 * - Read and write access
236 * - Access are handled by the memory controller according to MSEL
237 * - Not used for atomic operations
238 * - No data pipelining is done
241 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
246 #define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
251 /* With a 64 MB DIMM, the OR2 is configured as follows:
254 * - 4 internal banks per device
255 * - Row start address bit is A8 with PSDMR[PBI] = 0
256 * - 12 row address lines
257 * - Back-to-back page mode
258 * - Internal bank interleaving within save device enabled
260 #if (CFG_SDRAM_SIZE == 64)
261 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\
263 ORxS_ROWST_PBI0_A8 |\
265 #elif (CFG_SDRAM_SIZE == 16)
266 #define CFG_OR2_PRELIM (0xFF000CA0)
268 #error "INVALID SDRAM CONFIGURATION"
271 /*-----------------------------------------------------------------------
272 * PSDMR - 60x Bus SDRAM Mode Register
273 * Ref: Section 10.3.3 on page 10-21
274 *-----------------------------------------------------------------------
277 #if (CFG_SDRAM_SIZE == 64)
278 /* With a 64 MB DIMM, the PSDMR is configured as follows:
280 * - Bank Based Interleaving,
282 * - Address Multiplexing where A5 is output on A14 pin
283 * (A6 on A15, and so on),
284 * - use address pins A14-A16 as bank select,
285 * - A9 is output on SDA10 during an ACTIVATE command,
286 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
287 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
289 * - earliest timing for READ/WRITE command after ACTIVATE command is
291 * - earliest timing for PRECHARGE after last data was read is 1 clock,
292 * - earliest timing for PRECHARGE after last data was written is 1 clock,
293 * - CAS Latency is 2.
295 #define CFG_PSDMR (PSDMR_RFEN |\
296 PSDMR_SDAM_A14_IS_A5 |\
297 PSDMR_BSMA_A14_A16 |\
298 PSDMR_SDA10_PBI0_A9 |\
305 #elif (CFG_SDRAM_SIZE == 16)
306 /* With a 16 MB DIMM, the PSDMR is configured as follows:
308 * configuration parameters found in Motorola documentation
310 #define CFG_PSDMR (0x016EB452)
312 #error "INVALID SDRAM CONFIGURATION"
316 #define RS232EN_1 0x02000002
317 #define RS232EN_2 0x01000001
318 #define FETHIEN 0x08000008
319 #define FETH_RST 0x04000004
321 #define CFG_INIT_RAM_ADDR CFG_IMMR
322 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
323 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
324 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
325 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
329 /*#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
330 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
331 ( HRCW_BMS | HRCW_APPC10 ) |\
332 ( HRCW_MODCK_H0101 ) \
336 /* This value should actually be situated in the first 256 bytes of the FLASH
337 which on the standard MPC8266ADS board is at address 0xFF800000
338 The linker script places it at 0xFFF00000 instead.
340 It still works, however, as long as the ADS board jumper JP3 is set to
341 position 2-3 so the board is using the BCSR as Hardware Configuration Word
343 If you want to use the one defined here instead, ust copy the first 256 bytes from
344 0xfff00000 to 0xff800000 (for 8MB flash)
349 #define CFG_HRCW_MASTER 0x0cb23645
352 #define CFG_HRCW_SLAVE1 0
353 #define CFG_HRCW_SLAVE2 0
354 #define CFG_HRCW_SLAVE3 0
355 #define CFG_HRCW_SLAVE4 0
356 #define CFG_HRCW_SLAVE5 0
357 #define CFG_HRCW_SLAVE6 0
358 #define CFG_HRCW_SLAVE7 0
360 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
361 #define BOOTFLAG_WARM 0x02 /* Software reboot */
363 #define CFG_MONITOR_BASE TEXT_BASE
364 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
368 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
369 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
370 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
373 # define CFG_ENV_IS_IN_FLASH 1
374 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
375 # define CFG_ENV_SECT_SIZE 0x40000
377 # define CFG_ENV_IS_IN_NVRAM 1
378 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
379 # define CFG_ENV_SIZE 0x200
380 #endif /* CFG_RAMBOOT */
383 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
384 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
385 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
389 #define CFG_HID0_INIT 0
390 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
394 #define CFG_SYPCR 0xFFFFFFC3
395 #define CFG_BCR 0x100C0000
396 #define CFG_SIUMCR 0x0A200000
397 #define CFG_SCCR 0x00000000
398 #define CFG_BR0_PRELIM 0xFF801801
399 #define CFG_OR0_PRELIM 0xFF800836
400 #define CFG_BR1_PRELIM 0x04501801
401 #define CFG_OR1_PRELIM 0xFFFF8010
404 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
405 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
407 /*#define CFG_PSDMR 0x016EB452*/
408 #define CFG_MPTPR 0x00001900
409 #define CFG_PSRT 0x00000021
411 #define CFG_RESET_ADDRESS 0x04400000
413 #endif /* __CONFIG_H */