git.sur5r.net Git - u-boot/blob - include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * mpc8313epb board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1
  33 #define CONFIG_MPC83XX          1
  34 #define CONFIG_MPC831X          1
  35 #define CONFIG_MPC8313          1
  36 #define CONFIG_MPC8313ERDB      1
  37
  38 #define CONFIG_PCI
  39 #define CONFIG_83XX_GENERIC_PCI
  40
  41 #define CONFIG_MISC_INIT_R
  42
  43 /*
  44  * On-board devices
  45  *
  46  * TSEC1 is VSC switch
  47  * TSEC2 is SoC TSEC
  48  */
  49 #define CONFIG_VSC7385_ENET
  50 #define CONFIG_TSEC2
  51
  52 #ifdef CONFIG_SYS_66MHZ
  53 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  54 #elif defined(CONFIG_SYS_33MHZ)
  55 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  56 #else
  57 #error Unknown oscillator frequency.
  58 #endif
  59
  60 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  61
  62 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  63
  64 #define CONFIG_SYS_IMMR         0xE0000000
  65
  66 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  67 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  68 #endif
  69
  70 #define CONFIG_SYS_MEMTEST_START        0x00001000
  71 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  72
  73 /* Early revs of this board will lock up hard when attempting
  74  * to access the PMC registers, unless a JTAG debugger is
  75  * connected, or some resistor modifications are made.
  76  */
  77 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  78
  79 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  80 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  81
  82 /*
  83  * Device configurations
  84  */
  85
  86 /* Vitesse 7385 */
  87
  88 #ifdef CONFIG_VSC7385_ENET
  89
  90 #define CONFIG_TSEC1
  91
  92 /* The flash address and size of the VSC7385 firmware image */
  93 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  94 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  95
  96 #endif
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
 102 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 103 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 104
 105 /*
 106  * Manually set up DDR parameters, as this board does not
 107  * seem to have the SPD connected to I2C.
 108  */
 109 #define CONFIG_SYS_DDR_SIZE             128             /* MB */
 110 #define CONFIG_SYS_DDR_CONFIG           ( CSCONFIG_EN \
 111                                 | 0x00010000 /* TODO */ \
 112                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 113                                 /* 0x80010102 */
 114
 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 116 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 117                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 118                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 119                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 120                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 121                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 122                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 123                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 124                                 /* 0x00220802 */
 125 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 126                                 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 127                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 128                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 129                                 | (10 << TIMING_CFG1_REFREC_SHIFT ) \
 130                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 131                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 132                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 133                                 /* 0x3835a322 */
 134 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 135                                 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
 136                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 137                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 138                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 139                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 140                                 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 141                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 142 #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 143                                 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 144                                 /* 0x05100500 */
 145 #if defined(CONFIG_DDR_2T_TIMING)
 146 #define CONFIG_SYS_SDRAM_CFG            ( SDRAM_CFG_SREN \
 147                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 148                                 | SDRAM_CFG_2T_EN \
 149                                 | SDRAM_CFG_DBW_32 )
 150 #else
 151 #define CONFIG_SYS_SDRAM_CFG            ( SDRAM_CFG_SREN \
 152                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 153                                 | SDRAM_CFG_32_BE )
 154                                 /* 0x43080000 */
 155 #endif
 156 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 157 /* set burst length to 8 for 32-bit data path */
 158 #define CONFIG_SYS_DDR_MODE             ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 159                                 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
 160                                 /* 0x44480632 */
 161 #define CONFIG_SYS_DDR_MODE_2           0x8000C000
 162
 163 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 164                                 /*0x02000000*/
 165 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
 166                                 | DDRCDR_PZ_NOMZ \
 167                                 | DDRCDR_NZ_NOMZ \
 168                                 | DDRCDR_M_ODR )
 169
 170 /*
 171  * FLASH on the Local Bus
 172  */
 173 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 174 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 175 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 176 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 177 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 178 #define CONFIG_SYS_FLASH_EMPTY_INFO                     /* display empty sectors */
 179 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE               /* buffer up multiple bytes */
 180
 181 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 182                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
 183                                 BR_V)                   /* valid */
 184 #define CONFIG_SYS_NOR_OR_PRELIM        ( 0xFF800000            /* 8 MByte */ \
 185                                 | OR_GPCM_XACS \
 186                                 | OR_GPCM_SCY_9 \
 187                                 | OR_GPCM_EHTR \
 188                                 | OR_GPCM_EAD )
 189                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 190 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 191 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000017      /* 16 MB window size */
 192
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 194 #define CONFIG_SYS_MAX_FLASH_SECT       135             /* sectors per device */
 195
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 198
 199 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 200
 201 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
 202 #define CONFIG_SYS_RAMBOOT
 203 #endif
 204
 205 #define CONFIG_SYS_INIT_RAM_LOCK        1
 206 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
 207 #define CONFIG_SYS_INIT_RAM_END 0x1000          /* End of used area in RAM*/
 208
 209 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 210 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 211 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 212
 213 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 214 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 215 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 216
 217 /*
 218  * Local Bus LCRR and LBCR regs
 219  */
 220 #define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
 221 #define CONFIG_SYS_LBC_LBCR     ( 0x00040000 /* TODO */ \
 222                         | (0xFF << LBCR_BMT_SHIFT) \
 223                         | 0xF ) /* 0x0004ff0f */
 224
 225 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */   /* LB refresh timer prescal, 266MHz/32 */
 226
 227 /* drivers/mtd/nand/nand.c */
 228 #ifdef CONFIG_NAND_SPL
 229 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 230 #else
 231 #define CONFIG_SYS_NAND_BASE            0xE2800000
 232 #endif
 233
 234 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 235 #define CONFIG_MTD_NAND_VERIFY_WRITE
 236 #define CONFIG_CMD_NAND 1
 237 #define CONFIG_NAND_FSL_ELBC 1
 238 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 239
 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 241 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 242 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 243 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 244 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 245
 246 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
 247                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 248                                 | BR_PS_8               /* Port Size = 8 bit */ \
 249                                 | BR_MS_FCM             /* MSEL = FCM */ \
 250                                 | BR_V )                /* valid */
 251 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFF8000            /* length 32K */ \
 252                                 | OR_FCM_CSCT \
 253                                 | OR_FCM_CST \
 254                                 | OR_FCM_CHT \
 255                                 | OR_FCM_SCY_1 \
 256                                 | OR_FCM_TRLX \
 257                                 | OR_FCM_EHTR )
 258                                 /* 0xFFFF8396 */
 259
 260 #ifdef CONFIG_NAND_U_BOOT
 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 263 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 264 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 265 #else
 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 268 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 269 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 270 #endif
 271
 272 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 273 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E      /* 32KB  */
 274
 275 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 276 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 277
 278 /* local bus read write buffer mapping */
 279 #define CONFIG_SYS_BR3_PRELIM           0xFA000801      /* map at 0xFA000000 */
 280 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8FF7      /* 32kB */
 281 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xFA000000
 282 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E      /* 32KB  */
 283
 284 /* Vitesse 7385 */
 285
 286 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 287
 288 #ifdef CONFIG_VSC7385_ENET
 289
 290 #define CONFIG_SYS_BR2_PRELIM           0xf0000801      /* VSC7385 Base address */
 291 #define CONFIG_SYS_OR2_PRELIM           0xfffe09ff      /* VSC7385, 128K bytes*/
 292 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
 293 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* Access window size 128K */
 294
 295 #endif
 296
 297 /* pass open firmware flat tree */
 298 #define CONFIG_OF_LIBFDT        1
 299 #define CONFIG_OF_BOARD_SETUP   1
 300 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 301
 302 /*
 303  * Serial Port
 304  */
 305 #define CONFIG_CONS_INDEX       1
 306 #define CONFIG_SYS_NS16550
 307 #define CONFIG_SYS_NS16550_SERIAL
 308 #define CONFIG_SYS_NS16550_REG_SIZE     1
 309
 310 #define CONFIG_SYS_BAUDRATE_TABLE       \
 311         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 312
 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 315
 316 /* Use the HUSH parser */
 317 #define CONFIG_SYS_HUSH_PARSER
 318 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 319
 320 /* I2C */
 321 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 322 #define CONFIG_FSL_I2C
 323 #define CONFIG_I2C_MULTI_BUS
 324 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 325 #define CONFIG_SYS_I2C_SLAVE            0x7F
 326 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
 327 #define CONFIG_SYS_I2C_OFFSET           0x3000
 328 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 329
 330 /*
 331  * General PCI
 332  * Addresses are mapped 1-1.
 333  */
 334 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 335 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 336 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 337 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 338 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 339 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 340 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 341 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 342 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 343
 344 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 345 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 346
 347 /*
 348  * TSEC
 349  */
 350 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 351
 352 #define CONFIG_NET_MULTI
 353 #define CONFIG_GMII                     /* MII PHY management */
 354
 355 #ifdef CONFIG_TSEC1
 356 #define CONFIG_HAS_ETH0
 357 #define CONFIG_TSEC1_NAME       "TSEC0"
 358 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 359 #define TSEC1_PHY_ADDR          0x1c
 360 #define TSEC1_FLAGS             TSEC_GIGABIT
 361 #define TSEC1_PHYIDX            0
 362 #endif
 363
 364 #ifdef CONFIG_TSEC2
 365 #define CONFIG_HAS_ETH1
 366 #define CONFIG_TSEC2_NAME       "TSEC1"
 367 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 368 #define TSEC2_PHY_ADDR          4
 369 #define TSEC2_FLAGS             TSEC_GIGABIT
 370 #define TSEC2_PHYIDX            0
 371 #endif
 372
 373
 374 /* Options are: TSEC[0-1] */
 375 #define CONFIG_ETHPRIME                 "TSEC1"
 376
 377 /*
 378  * Configure on-board RTC
 379  */
 380 #define CONFIG_RTC_DS1337
 381 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 382
 383 /*
 384  * Environment
 385  */
 386 #if defined(CONFIG_NAND_U_BOOT)
 387         #define CONFIG_ENV_IS_IN_NAND   1
 388         #define CONFIG_ENV_OFFSET               (512 * 1024)
 389         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 390         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 391         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 392         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 393         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 394 #elif !defined(CONFIG_SYS_RAMBOOT)
 395         #define CONFIG_ENV_IS_IN_FLASH  1
 396         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 397         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 398         #define CONFIG_ENV_SIZE         0x2000
 399
 400 /* Address and size of Redundant Environment Sector */
 401 #else
 402         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 403         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 404         #define CONFIG_ENV_SIZE         0x2000
 405 #endif
 406
 407 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 408 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 409
 410 /*
 411  * BOOTP options
 412  */
 413 #define CONFIG_BOOTP_BOOTFILESIZE
 414 #define CONFIG_BOOTP_BOOTPATH
 415 #define CONFIG_BOOTP_GATEWAY
 416 #define CONFIG_BOOTP_HOSTNAME
 417
 418
 419 /*
 420  * Command line configuration.
 421  */
 422 #include <config_cmd_default.h>
 423
 424 #define CONFIG_CMD_PING
 425 #define CONFIG_CMD_DHCP
 426 #define CONFIG_CMD_I2C
 427 #define CONFIG_CMD_MII
 428 #define CONFIG_CMD_DATE
 429 #define CONFIG_CMD_PCI
 430
 431 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 432     #undef CONFIG_CMD_SAVEENV
 433     #undef CONFIG_CMD_LOADS
 434 #endif
 435
 436 #define CONFIG_CMDLINE_EDITING 1
 437
 438
 439 /*
 440  * Miscellaneous configurable options
 441  */
 442 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 443 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 444 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 445 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 446
 447 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 448 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 449 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 450 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 451
 452 /*
 453  * For booting Linux, the board info and command line data
 454  * have to be in the first 8 MB of memory, since this is
 455  * the maximum mapped by the Linux kernel during initialization.
 456  */
 457 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 458
 459 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 460
 461 #ifdef CONFIG_SYS_66MHZ
 462
 463 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 464 /* 0x62040000 */
 465 #define CONFIG_SYS_HRCW_LOW (\
 466         0x20000000 /* reserved, must be set */ |\
 467         HRCWL_DDRCM |\
 468         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 469         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 470         HRCWL_CSB_TO_CLKIN_2X1 |\
 471         HRCWL_CORE_TO_CSB_2X1)
 472
 473 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 474
 475 #elif defined(CONFIG_SYS_33MHZ)
 476
 477 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 478 /* 0x65040000 */
 479 #define CONFIG_SYS_HRCW_LOW (\
 480         0x20000000 /* reserved, must be set */ |\
 481         HRCWL_DDRCM |\
 482         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 483         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 484         HRCWL_CSB_TO_CLKIN_5X1 |\
 485         HRCWL_CORE_TO_CSB_2X1)
 486
 487 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 488
 489 #endif
 490
 491 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 492         HRCWH_PCI_HOST |\
 493         HRCWH_PCI1_ARBITER_ENABLE |\
 494         HRCWH_CORE_ENABLE |\
 495         HRCWH_BOOTSEQ_DISABLE |\
 496         HRCWH_SW_WATCHDOG_DISABLE |\
 497         HRCWH_TSEC1M_IN_RGMII |\
 498         HRCWH_TSEC2M_IN_RGMII |\
 499         HRCWH_BIG_ENDIAN)
 500
 501 #ifdef CONFIG_NAND_SPL
 502 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 503                        HRCWH_FROM_0XFFF00100 |\
 504                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 505                        HRCWH_RL_EXT_NAND)
 506 #else
 507 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 508                        HRCWH_FROM_0X00000100 |\
 509                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 510                        HRCWH_RL_EXT_LEGACY)
 511 #endif
 512
 513 /* System IO Config */
 514 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 515 #define CONFIG_SYS_SICRL        SICRL_USBDR                     /* Enable Internal USB Phy  */
 516
 517 #define CONFIG_SYS_HID0_INIT    0x000000000
 518 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 519                          HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 520
 521 #define CONFIG_SYS_HID2 HID2_HBE
 522
 523 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 524
 525 /* DDR @ 0x00000000 */
 526 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 527 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 528
 529 /* PCI @ 0x80000000 */
 530 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 531 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 532 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 533 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 534
 535 /* PCI2 not supported on 8313 */
 536 #define CONFIG_SYS_IBAT3L       (0)
 537 #define CONFIG_SYS_IBAT3U       (0)
 538 #define CONFIG_SYS_IBAT4L       (0)
 539 #define CONFIG_SYS_IBAT4U       (0)
 540
 541 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 542 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 543 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 544
 545 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 546 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 547 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 548
 549 #define CONFIG_SYS_IBAT7L       (0)
 550 #define CONFIG_SYS_IBAT7U       (0)
 551
 552 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 553 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 554 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 555 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 556 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 557 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 558 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 559 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 560 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 561 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 562 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 563 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 564 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 565 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 566 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 567 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 568
 569 /*
 570  * Internal Definitions
 571  *
 572  * Boot Flags
 573  */
 574 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 575 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 576
 577 /*
 578  * Environment Configuration
 579  */
 580 #define CONFIG_ENV_OVERWRITE
 581
 582 #define CONFIG_ETHADDR          00:E0:0C:00:95:01
 583 #define CONFIG_ETH1ADDR         00:E0:0C:00:95:02
 584
 585 #define CONFIG_IPADDR           10.0.0.2
 586 #define CONFIG_SERVERIP         10.0.0.1
 587 #define CONFIG_GATEWAYIP        10.0.0.1
 588 #define CONFIG_NETMASK          255.0.0.0
 589 #define CONFIG_NETDEV           eth1
 590
 591 #define CONFIG_HOSTNAME         mpc8313erdb
 592 #define CONFIG_ROOTPATH         /nfs/root/path
 593 #define CONFIG_BOOTFILE         uImage
 594 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 595 #define CONFIG_FDTFILE          mpc8313erdb.dtb
 596
 597 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 598 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 599 #define CONFIG_BAUDRATE         115200
 600
 601 #define XMK_STR(x)      #x
 602 #define MK_STR(x)       XMK_STR(x)
 603
 604 #define CONFIG_EXTRA_ENV_SETTINGS \
 605         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 606         "ethprime=TSEC1\0"                                              \
 607         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 608         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 609                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 610                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 611                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 612                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 613                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 614         "fdtaddr=400000\0"                                              \
 615         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 616         "console=ttyS0\0"                                               \
 617         "setbootargs=setenv bootargs "                                  \
 618                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 619         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 620                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 621                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 622
 623 #define CONFIG_NFSBOOTCOMMAND                                           \
 624         "setenv rootdev /dev/nfs;"                                      \
 625         "run setbootargs;"                                              \
 626         "run setipargs;"                                                \
 627         "tftp $loadaddr $bootfile;"                                     \
 628         "tftp $fdtaddr $fdtfile;"                                       \
 629         "bootm $loadaddr - $fdtaddr"
 630
 631 #define CONFIG_RAMBOOTCOMMAND                                           \
 632         "setenv rootdev /dev/ram;"                                      \
 633         "run setbootargs;"                                              \
 634         "tftp $ramdiskaddr $ramdiskfile;"                               \
 635         "tftp $loadaddr $bootfile;"                                     \
 636         "tftp $fdtaddr $fdtfile;"                                       \
 637         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 638
 639 #undef MK_STR
 640 #undef XMK_STR
 641
 642 #endif  /* __CONFIG_H */