git.sur5r.net Git - u-boot/blob - include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * mpc8313epb board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1
  33 #define CONFIG_MPC83xx          1
  34 #define CONFIG_MPC831x          1
  35 #define CONFIG_MPC8313          1
  36 #define CONFIG_MPC8313ERDB      1
  37
  38 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  39 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  41 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  44
  45 #ifdef CONFIG_NAND_U_BOOT
  46 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  47 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  48 #ifdef CONFIG_NAND_SPL
  49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  50 #endif /* CONFIG_NAND_SPL */
  51 #endif /* CONFIG_NAND_U_BOOT */
  52
  53 #ifndef CONFIG_SYS_TEXT_BASE
  54 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  55 #endif
  56
  57 #ifndef CONFIG_SYS_MONITOR_BASE
  58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  59 #endif
  60
  61 #define CONFIG_PCI
  62 #define CONFIG_FSL_ELBC 1
  63
  64 #define CONFIG_MISC_INIT_R
  65
  66 /*
  67  * On-board devices
  68  *
  69  * TSEC1 is VSC switch
  70  * TSEC2 is SoC TSEC
  71  */
  72 #define CONFIG_VSC7385_ENET
  73 #define CONFIG_TSEC2
  74
  75 #ifdef CONFIG_SYS_66MHZ
  76 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  77 #elif defined(CONFIG_SYS_33MHZ)
  78 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  79 #else
  80 #error Unknown oscillator frequency.
  81 #endif
  82
  83 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  84
  85 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f */
  86 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
  87
  88 #define CONFIG_SYS_IMMR         0xE0000000
  89
  90 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  91 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  92 #endif
  93
  94 #define CONFIG_SYS_MEMTEST_START        0x00001000
  95 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  96
  97 /* Early revs of this board will lock up hard when attempting
  98  * to access the PMC registers, unless a JTAG debugger is
  99  * connected, or some resistor modifications are made.
 100  */
 101 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 102
 103 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 104 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 105
 106 /*
 107  * Device configurations
 108  */
 109
 110 /* Vitesse 7385 */
 111
 112 #ifdef CONFIG_VSC7385_ENET
 113
 114 #define CONFIG_TSEC1
 115
 116 /* The flash address and size of the VSC7385 firmware image */
 117 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 118 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 119
 120 #endif
 121
 122 /*
 123  * DDR Setup
 124  */
 125 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 126 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 128
 129 /*
 130  * Manually set up DDR parameters, as this board does not
 131  * seem to have the SPD connected to I2C.
 132  */
 133 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 134 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 135                                 | CSCONFIG_ODT_RD_NEVER \
 136                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 137                                 | CSCONFIG_ROW_BIT_13 \
 138                                 | CSCONFIG_COL_BIT_10)
 139                                 /* 0x80010102 */
 140
 141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 142 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 143                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 144                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 145                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 146                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 147                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 148                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 149                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 150                                 /* 0x00220802 */
 151 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 152                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 153                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 154                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 155                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 156                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 157                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 158                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 159                                 /* 0x3835a322 */
 160 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 161                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 162                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 163                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 164                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 165                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 166                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 167                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 168 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 169                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 170                                 /* 0x05100500 */
 171 #if defined(CONFIG_DDR_2T_TIMING)
 172 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 173                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 174                                 | SDRAM_CFG_DBW_32 \
 175                                 | SDRAM_CFG_2T_EN)
 176                                 /* 0x43088000 */
 177 #else
 178 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 179                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 180                                 | SDRAM_CFG_DBW_32)
 181                                 /* 0x43080000 */
 182 #endif
 183 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 184 /* set burst length to 8 for 32-bit data path */
 185 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 186                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 187                                 /* 0x44480632 */
 188 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 189
 190 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 191                                 /*0x02000000*/
 192 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 193                                 | DDRCDR_PZ_NOMZ \
 194                                 | DDRCDR_NZ_NOMZ \
 195                                 | DDRCDR_M_ODR)
 196
 197 /*
 198  * FLASH on the Local Bus
 199  */
 200 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 201 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 202 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 203 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 204 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 205 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 207
 208 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 209                                         | BR_PS_16      /* 16 bit port */ \
 210                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 211                                         | BR_V)         /* valid */
 212 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 213                                 | OR_GPCM_XACS \
 214                                 | OR_GPCM_SCY_9 \
 215                                 | OR_GPCM_EHTR \
 216                                 | OR_GPCM_EAD)
 217                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 218                                         /* window base at flash base */
 219 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 220                                         /* 16 MB window size */
 221 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 222
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 225
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 228
 229 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 230         !defined(CONFIG_NAND_SPL)
 231 #define CONFIG_SYS_RAMBOOT
 232 #endif
 233
 234 #define CONFIG_SYS_INIT_RAM_LOCK        1
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 237
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 239                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 243 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 244 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 245
 246 /*
 247  * Local Bus LCRR and LBCR regs
 248  */
 249 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 250 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 251 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 252                                 | (0xFF << LBCR_BMT_SHIFT) \
 253                                 | 0xF)  /* 0x0004ff0f */
 254
 255                                 /* LB refresh timer prescal, 266MHz/32 */
 256 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 257
 258 /* drivers/mtd/nand/nand.c */
 259 #ifdef CONFIG_NAND_SPL
 260 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 261 #else
 262 #define CONFIG_SYS_NAND_BASE            0xE2800000
 263 #endif
 264
 265 #define CONFIG_MTD_DEVICE
 266 #define CONFIG_MTD_PARTITION
 267 #define CONFIG_CMD_MTDPARTS
 268 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
 269 #define MTDPARTS_DEFAULT                \
 270         "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
 271
 272 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 273 #define CONFIG_MTD_NAND_VERIFY_WRITE
 274 #define CONFIG_CMD_NAND 1
 275 #define CONFIG_NAND_FSL_ELBC 1
 276 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 277 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 278
 279
 280 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 281                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 282                                 | BR_PS_8               /* 8 bit port */ \
 283                                 | BR_MS_FCM             /* MSEL = FCM */ \
 284                                 | BR_V)                 /* valid */
 285 #define CONFIG_SYS_NAND_OR_PRELIM       \
 286                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 287                                 | OR_FCM_CSCT \
 288                                 | OR_FCM_CST \
 289                                 | OR_FCM_CHT \
 290                                 | OR_FCM_SCY_1 \
 291                                 | OR_FCM_TRLX \
 292                                 | OR_FCM_EHTR)
 293                                 /* 0xFFFF8396 */
 294
 295 #ifdef CONFIG_NAND_U_BOOT
 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 298 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 299 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 300 #else
 301 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 302 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 303 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 304 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 305 #endif
 306
 307 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 308 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 309
 310 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 311 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 312
 313 /* local bus write LED / read status buffer (BCSR) mapping */
 314 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 315 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 316                                         /* map at 0xFA000000 on LCS3 */
 317 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 318                                         | BR_PS_8       /* 8 bit port */ \
 319                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 320                                         | BR_V)         /* valid */
 321                                         /* 0xFA000801 */
 322 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 323                                         | OR_GPCM_CSNT \
 324                                         | OR_GPCM_ACS_DIV2 \
 325                                         | OR_GPCM_XACS \
 326                                         | OR_GPCM_SCY_15 \
 327                                         | OR_GPCM_TRLX_SET \
 328                                         | OR_GPCM_EHTR_SET \
 329                                         | OR_GPCM_EAD)
 330                                         /* 0xFFFF8FF7 */
 331 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 332 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 333
 334 /* Vitesse 7385 */
 335
 336 #ifdef CONFIG_VSC7385_ENET
 337
 338                                         /* VSC7385 Base address on LCS2 */
 339 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 340 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 341
 342 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 343                                         | BR_PS_8       /* 8 bit port */ \
 344                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 345                                         | BR_V)         /* valid */
 346 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 347                                         | OR_GPCM_CSNT \
 348                                         | OR_GPCM_XACS \
 349                                         | OR_GPCM_SCY_15 \
 350                                         | OR_GPCM_SETA \
 351                                         | OR_GPCM_TRLX_SET \
 352                                         | OR_GPCM_EHTR_SET \
 353                                         | OR_GPCM_EAD)
 354                                         /* 0xFFFE09FF */
 355
 356                                         /* Access window base at VSC7385 base */
 357 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 358 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 359
 360 #endif
 361
 362 /* pass open firmware flat tree */
 363 #define CONFIG_OF_LIBFDT        1
 364 #define CONFIG_OF_BOARD_SETUP   1
 365 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 366
 367 #define CONFIG_MPC83XX_GPIO 1
 368 #define CONFIG_CMD_GPIO 1
 369
 370 /*
 371  * Serial Port
 372  */
 373 #define CONFIG_CONS_INDEX       1
 374 #define CONFIG_SYS_NS16550
 375 #define CONFIG_SYS_NS16550_SERIAL
 376 #define CONFIG_SYS_NS16550_REG_SIZE     1
 377
 378 #define CONFIG_SYS_BAUDRATE_TABLE       \
 379         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 380
 381 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 382 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 383
 384 /* Use the HUSH parser */
 385 #define CONFIG_SYS_HUSH_PARSER
 386
 387 /* I2C */
 388 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 389 #define CONFIG_FSL_I2C
 390 #define CONFIG_I2C_MULTI_BUS
 391 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 392 #define CONFIG_SYS_I2C_SLAVE    0x7F
 393 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
 394 #define CONFIG_SYS_I2C_OFFSET   0x3000
 395 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 396
 397 /*
 398  * General PCI
 399  * Addresses are mapped 1-1.
 400  */
 401 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 402 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 403 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 404 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 405 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 406 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 407 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 408 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 409 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 410
 411 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 412 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 413
 414 /*
 415  * TSEC
 416  */
 417 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 418
 419 #define CONFIG_GMII                     /* MII PHY management */
 420
 421 #ifdef CONFIG_TSEC1
 422 #define CONFIG_HAS_ETH0
 423 #define CONFIG_TSEC1_NAME       "TSEC0"
 424 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 425 #define TSEC1_PHY_ADDR          0x1c
 426 #define TSEC1_FLAGS             TSEC_GIGABIT
 427 #define TSEC1_PHYIDX            0
 428 #endif
 429
 430 #ifdef CONFIG_TSEC2
 431 #define CONFIG_HAS_ETH1
 432 #define CONFIG_TSEC2_NAME       "TSEC1"
 433 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 434 #define TSEC2_PHY_ADDR          4
 435 #define TSEC2_FLAGS             TSEC_GIGABIT
 436 #define TSEC2_PHYIDX            0
 437 #endif
 438
 439
 440 /* Options are: TSEC[0-1] */
 441 #define CONFIG_ETHPRIME                 "TSEC1"
 442
 443 /*
 444  * Configure on-board RTC
 445  */
 446 #define CONFIG_RTC_DS1337
 447 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 448
 449 /*
 450  * Environment
 451  */
 452 #if defined(CONFIG_NAND_U_BOOT)
 453         #define CONFIG_ENV_IS_IN_NAND   1
 454         #define CONFIG_ENV_OFFSET               (512 * 1024)
 455         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 456         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 457         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 458         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 459         #define CONFIG_ENV_OFFSET_REDUND        \
 460                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 461 #elif !defined(CONFIG_SYS_RAMBOOT)
 462         #define CONFIG_ENV_IS_IN_FLASH  1
 463         #define CONFIG_ENV_ADDR         \
 464                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 465         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 466         #define CONFIG_ENV_SIZE         0x2000
 467
 468 /* Address and size of Redundant Environment Sector */
 469 #else
 470         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 471         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 472         #define CONFIG_ENV_SIZE         0x2000
 473 #endif
 474
 475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 477
 478 /*
 479  * BOOTP options
 480  */
 481 #define CONFIG_BOOTP_BOOTFILESIZE
 482 #define CONFIG_BOOTP_BOOTPATH
 483 #define CONFIG_BOOTP_GATEWAY
 484 #define CONFIG_BOOTP_HOSTNAME
 485
 486
 487 /*
 488  * Command line configuration.
 489  */
 490 #include <config_cmd_default.h>
 491
 492 #define CONFIG_CMD_PING
 493 #define CONFIG_CMD_DHCP
 494 #define CONFIG_CMD_I2C
 495 #define CONFIG_CMD_MII
 496 #define CONFIG_CMD_DATE
 497 #define CONFIG_CMD_PCI
 498
 499 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 500     #undef CONFIG_CMD_SAVEENV
 501     #undef CONFIG_CMD_LOADS
 502 #endif
 503
 504 #define CONFIG_CMDLINE_EDITING 1
 505 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 506
 507 /*
 508  * Miscellaneous configurable options
 509  */
 510 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 511 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 512 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 513 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 514
 515                                                 /* Print Buffer Size */
 516 #define CONFIG_SYS_PBSIZE       \
 517                         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 518 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 519                                 /* Boot Argument Buffer Size */
 520 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 521 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 522
 523 /*
 524  * For booting Linux, the board info and command line data
 525  * have to be in the first 256 MB of memory, since this is
 526  * the maximum mapped by the Linux kernel during initialization.
 527  */
 528                                 /* Initial Memory map for Linux*/
 529 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 530
 531 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 532
 533 #ifdef CONFIG_SYS_66MHZ
 534
 535 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 536 /* 0x62040000 */
 537 #define CONFIG_SYS_HRCW_LOW (\
 538         0x20000000 /* reserved, must be set */ |\
 539         HRCWL_DDRCM |\
 540         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 541         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 542         HRCWL_CSB_TO_CLKIN_2X1 |\
 543         HRCWL_CORE_TO_CSB_2X1)
 544
 545 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 546
 547 #elif defined(CONFIG_SYS_33MHZ)
 548
 549 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 550 /* 0x65040000 */
 551 #define CONFIG_SYS_HRCW_LOW (\
 552         0x20000000 /* reserved, must be set */ |\
 553         HRCWL_DDRCM |\
 554         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 555         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 556         HRCWL_CSB_TO_CLKIN_5X1 |\
 557         HRCWL_CORE_TO_CSB_2X1)
 558
 559 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 560
 561 #endif
 562
 563 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 564         HRCWH_PCI_HOST |\
 565         HRCWH_PCI1_ARBITER_ENABLE |\
 566         HRCWH_CORE_ENABLE |\
 567         HRCWH_BOOTSEQ_DISABLE |\
 568         HRCWH_SW_WATCHDOG_DISABLE |\
 569         HRCWH_TSEC1M_IN_RGMII |\
 570         HRCWH_TSEC2M_IN_RGMII |\
 571         HRCWH_BIG_ENDIAN)
 572
 573 #ifdef CONFIG_NAND_SPL
 574 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 575                        HRCWH_FROM_0XFFF00100 |\
 576                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 577                        HRCWH_RL_EXT_NAND)
 578 #else
 579 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 580                        HRCWH_FROM_0X00000100 |\
 581                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 582                        HRCWH_RL_EXT_LEGACY)
 583 #endif
 584
 585 /* System IO Config */
 586 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 587                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 588 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 589
 590 #define CONFIG_SYS_HID0_INIT    0x000000000
 591 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 592                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 593                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 594
 595 #define CONFIG_SYS_HID2 HID2_HBE
 596
 597 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 598
 599 /* DDR @ 0x00000000 */
 600 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 601 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 602                                 | BATU_BL_256M \
 603                                 | BATU_VS \
 604                                 | BATU_VP)
 605
 606 /* PCI @ 0x80000000 */
 607 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 608 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 609                                 | BATU_BL_256M \
 610                                 | BATU_VS \
 611                                 | BATU_VP)
 612 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 613                                 | BATL_PP_RW \
 614                                 | BATL_CACHEINHIBIT \
 615                                 | BATL_GUARDEDSTORAGE)
 616 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 617                                 | BATU_BL_256M \
 618                                 | BATU_VS \
 619                                 | BATU_VP)
 620
 621 /* PCI2 not supported on 8313 */
 622 #define CONFIG_SYS_IBAT3L       (0)
 623 #define CONFIG_SYS_IBAT3U       (0)
 624 #define CONFIG_SYS_IBAT4L       (0)
 625 #define CONFIG_SYS_IBAT4U       (0)
 626
 627 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 628 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 629                                 | BATL_PP_RW \
 630                                 | BATL_CACHEINHIBIT \
 631                                 | BATL_GUARDEDSTORAGE)
 632 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 633                                 | BATU_BL_256M \
 634                                 | BATU_VS \
 635                                 | BATU_VP)
 636
 637 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 638 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 639 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 640
 641 #define CONFIG_SYS_IBAT7L       (0)
 642 #define CONFIG_SYS_IBAT7U       (0)
 643
 644 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 645 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 646 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 647 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 648 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 649 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 650 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 651 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 652 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 653 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 654 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 655 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 656 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 657 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 658 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 659 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 660
 661 /*
 662  * Environment Configuration
 663  */
 664 #define CONFIG_ENV_OVERWRITE
 665
 666 #define CONFIG_NETDEV           "eth1"
 667
 668 #define CONFIG_HOSTNAME         mpc8313erdb
 669 #define CONFIG_ROOTPATH         "/nfs/root/path"
 670 #define CONFIG_BOOTFILE         "uImage"
 671                                 /* U-Boot image on TFTP server */
 672 #define CONFIG_UBOOTPATH        "u-boot.bin"
 673 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 674
 675                                 /* default location for tftp and bootm */
 676 #define CONFIG_LOADADDR         800000
 677 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 678 #define CONFIG_BAUDRATE         115200
 679
 680 #define XMK_STR(x)      #x
 681 #define MK_STR(x)       XMK_STR(x)
 682
 683 #define CONFIG_EXTRA_ENV_SETTINGS \
 684         "netdev=" CONFIG_NETDEV "\0"                                    \
 685         "ethprime=TSEC1\0"                                              \
 686         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 687         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 688                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
 689                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "   \
 690                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
 691                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
 692                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
 693         "fdtaddr=780000\0"                                              \
 694         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 695         "console=ttyS0\0"                                               \
 696         "setbootargs=setenv bootargs "                                  \
 697                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 698         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 699                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 700                                                         "$netdev:off " \
 701                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 702
 703 #define CONFIG_NFSBOOTCOMMAND                                           \
 704         "setenv rootdev /dev/nfs;"                                      \
 705         "run setbootargs;"                                              \
 706         "run setipargs;"                                                \
 707         "tftp $loadaddr $bootfile;"                                     \
 708         "tftp $fdtaddr $fdtfile;"                                       \
 709         "bootm $loadaddr - $fdtaddr"
 710
 711 #define CONFIG_RAMBOOTCOMMAND                                           \
 712         "setenv rootdev /dev/ram;"                                      \
 713         "run setbootargs;"                                              \
 714         "tftp $ramdiskaddr $ramdiskfile;"                               \
 715         "tftp $loadaddr $bootfile;"                                     \
 716         "tftp $fdtaddr $fdtfile;"                                       \
 717         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 718
 719 #undef MK_STR
 720 #undef XMK_STR
 721
 722 #endif  /* __CONFIG_H */