2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
17 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
22 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
24 #ifndef CONFIG_SYS_CLK_FREQ
25 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
29 * Hardware Reset Configuration Word
31 #define CONFIG_SYS_HRCW_LOW (\
32 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
33 HRCWL_DDR_TO_SCB_CLK_2X1 |\
35 HRCWL_CSB_TO_CLKIN_2X1 |\
36 HRCWL_CORE_TO_CSB_2_5X1 |\
37 HRCWL_CE_PLL_VCO_DIV_2 |\
38 HRCWL_CE_PLL_DIV_1X1 |\
41 #define CONFIG_SYS_HRCW_HIGH (\
43 HRCWH_PCI1_ARBITER_ENABLE |\
45 HRCWH_FROM_0X00000100 |\
46 HRCWH_BOOTSEQ_DISABLE |\
47 HRCWH_SW_WATCHDOG_DISABLE |\
48 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 #define CONFIG_SYS_SICRL 0x00000000
60 #define CONFIG_SYS_IMMR 0xE0000000
65 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
66 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
67 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
68 #define CONFIG_SYS_SPCR_OPT 1
73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
77 #undef CONFIG_SPD_EEPROM
78 #if defined(CONFIG_SPD_EEPROM)
79 /* Determine DDR configuration from I2C interface
81 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
83 /* Manually set up DDR parameters
85 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
86 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
87 | CSCONFIG_ROW_BIT_13 \
90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91 | (0 << TIMING_CFG0_WRT_SHIFT) \
92 | (0 << TIMING_CFG0_RRT_SHIFT) \
93 | (0 << TIMING_CFG0_WWT_SHIFT) \
94 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
99 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
103 | (3 << TIMING_CFG1_REFREC_SHIFT) \
104 | (2 << TIMING_CFG1_WRREC_SHIFT) \
105 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106 | (2 << TIMING_CFG1_WRTORD_SHIFT))
108 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
109 | (31 << TIMING_CFG2_CPO_SHIFT) \
110 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
117 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
119 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
120 | (0x0232 << SDRAM_MODE_SD_SHIFT))
122 #define CONFIG_SYS_DDR_MODE2 0x8000c000
123 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
124 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
126 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
127 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
128 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
131 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
137 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
138 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
139 #define CONFIG_SYS_MEMTEST_END 0x03f00000
142 * The reserved memory
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
147 #define CONFIG_SYS_RAMBOOT
149 #undef CONFIG_SYS_RAMBOOT
152 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
153 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
154 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
157 * Initial RAM Base Address Setup
159 #define CONFIG_SYS_INIT_RAM_LOCK 1
160 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
161 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
162 #define CONFIG_SYS_GBL_DATA_OFFSET \
163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
166 * Local Bus Configuration & Clock Setup
168 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
169 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
170 #define CONFIG_SYS_LBC_LBCR 0x00000000
173 * FLASH on the Local Bus
175 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
176 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
177 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
178 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
179 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
181 /* Window base at flash base */
182 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
183 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
185 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
186 | BR_PS_16 /* 16 bit port */ \
187 | BR_MS_GPCM /* MSEL = GPCM */ \
189 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
203 #undef CONFIG_SYS_FLASH_CHECKSUM
208 #define CONFIG_CONS_INDEX 1
209 #define CONFIG_SYS_NS16550_SERIAL
210 #define CONFIG_SYS_NS16550_REG_SIZE 1
211 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
213 #define CONFIG_SYS_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
219 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
220 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
223 #define CONFIG_SYS_I2C
224 #define CONFIG_SYS_I2C_FSL
225 #define CONFIG_SYS_FSL_I2C_SPEED 400000
226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
228 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
231 * Config on-board EEPROM
233 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
240 * Addresses are mapped 1-1.
242 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
243 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
245 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
246 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
247 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
248 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
249 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
250 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
253 #define CONFIG_PCI_INDIRECT_BRIDGE
254 #define CONFIG_PCI_SKIP_HOST_BRIDGE
256 #undef CONFIG_EEPRO100
257 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
258 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
260 #endif /* CONFIG_PCI */
263 * QE UEC ethernet configuration
265 #define CONFIG_UEC_ETH
266 #define CONFIG_ETHPRIME "UEC0"
268 #define CONFIG_UEC_ETH1 /* ETH3 */
270 #ifdef CONFIG_UEC_ETH1
271 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
272 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
273 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
274 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
275 #define CONFIG_SYS_UEC1_PHY_ADDR 4
276 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
277 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
280 #define CONFIG_UEC_ETH2 /* ETH4 */
282 #ifdef CONFIG_UEC_ETH2
283 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
284 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
285 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
286 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
287 #define CONFIG_SYS_UEC2_PHY_ADDR 0
288 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
289 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
295 #ifndef CONFIG_SYS_RAMBOOT
296 #define CONFIG_ENV_ADDR \
297 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
298 #define CONFIG_ENV_SECT_SIZE 0x20000
299 #define CONFIG_ENV_SIZE 0x2000
301 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
302 #define CONFIG_ENV_SIZE 0x2000
305 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
306 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
311 #define CONFIG_BOOTP_BOOTFILESIZE
312 #define CONFIG_BOOTP_BOOTPATH
313 #define CONFIG_BOOTP_GATEWAY
314 #define CONFIG_BOOTP_HOSTNAME
317 * Command line configuration.
320 #undef CONFIG_WATCHDOG /* watchdog disabled */
323 * Miscellaneous configurable options
325 #define CONFIG_SYS_LONGHELP /* undef to save memory */
326 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
329 * For booting Linux, the board info and command line data
330 * have to be in the first 256 MB of memory, since this is
331 * the maximum mapped by the Linux kernel during initialization.
333 /* Initial Memory map for Linux */
334 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
335 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
340 #define CONFIG_SYS_HID0_INIT 0x000000000
341 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
342 HID0_ENABLE_INSTRUCTION_CACHE)
343 #define CONFIG_SYS_HID2 HID2_HBE
348 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
350 /* DDR: cache cacheable */
351 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
354 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
358 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
359 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
361 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
362 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
364 | BATL_CACHEINHIBIT \
365 | BATL_GUARDEDSTORAGE)
366 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
370 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
371 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
373 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
374 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
377 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
381 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
383 | BATL_CACHEINHIBIT \
384 | BATL_GUARDEDSTORAGE)
385 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
387 #define CONFIG_SYS_IBAT3L (0)
388 #define CONFIG_SYS_IBAT3U (0)
389 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
390 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
392 /* Stack in dcache: cacheable, no memory coherence */
393 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
394 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
398 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
399 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
402 /* PCI MEM space: cacheable */
403 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
406 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
410 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
411 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
412 /* PCI MMIO space: cache-inhibit and guarded */
413 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
415 | BATL_CACHEINHIBIT \
416 | BATL_GUARDEDSTORAGE)
417 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
421 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
422 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
424 #define CONFIG_SYS_IBAT5L (0)
425 #define CONFIG_SYS_IBAT5U (0)
426 #define CONFIG_SYS_IBAT6L (0)
427 #define CONFIG_SYS_IBAT6U (0)
428 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
429 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
430 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
431 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
434 /* Nothing in BAT7 */
435 #define CONFIG_SYS_IBAT7L (0)
436 #define CONFIG_SYS_IBAT7U (0)
437 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
438 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
440 #if (CONFIG_CMD_KGDB)
441 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
445 * Environment Configuration
447 #define CONFIG_ENV_OVERWRITE
449 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
450 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
452 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
453 * (see CONFIG_SYS_I2C_EEPROM) */
454 /* MAC address offset in I2C EEPROM */
455 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
457 #define CONFIG_NETDEV "eth1"
459 #define CONFIG_HOSTNAME mpc8323erdb
460 #define CONFIG_ROOTPATH "/nfsroot"
461 #define CONFIG_BOOTFILE "uImage"
462 /* U-Boot image on TFTP server */
463 #define CONFIG_UBOOTPATH "u-boot.bin"
464 #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
465 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
467 /* default location for tftp and bootm */
468 #define CONFIG_LOADADDR 800000
470 #define CONFIG_EXTRA_ENV_SETTINGS \
471 "netdev=" CONFIG_NETDEV "\0" \
472 "uboot=" CONFIG_UBOOTPATH "\0" \
473 "tftpflash=tftp $loadaddr $uboot;" \
474 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
476 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
478 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
480 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
482 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
485 "fdtfile=" CONFIG_FDTFILE "\0" \
486 "ramdiskaddr=1000000\0" \
487 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
489 "setbootargs=setenv bootargs " \
490 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
491 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
492 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
494 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
496 #define CONFIG_NFSBOOTCOMMAND \
497 "setenv rootdev /dev/nfs;" \
500 "tftp $loadaddr $bootfile;" \
501 "tftp $fdtaddr $fdtfile;" \
502 "bootm $loadaddr - $fdtaddr"
504 #define CONFIG_RAMBOOTCOMMAND \
505 "setenv rootdev /dev/ram;" \
507 "tftp $ramdiskaddr $ramdiskfile;" \
508 "tftp $loadaddr $bootfile;" \
509 "tftp $fdtaddr $fdtfile;" \
510 "bootm $loadaddr $ramdiskaddr $fdtaddr"
512 #endif /* __CONFIG_H */