2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
35 0xF001_0000-0xF001_FFFF Local bus expansion slot
36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
42 Bus Addr Part No. Description Length Location
43 ----------------------------------------------------------------
44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
46 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
59 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
60 #define CONFIG_SYS_LOWBOOT
64 * High Level Configuration Options
66 #define CONFIG_MPC83xx 1
67 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
68 #define CONFIG_MPC8349 /* MPC8349 specific */
70 #ifndef CONFIG_SYS_TEXT_BASE
71 #define CONFIG_SYS_TEXT_BASE 0xFEF00000
74 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
76 #define CONFIG_MISC_INIT_F
77 #define CONFIG_MISC_INIT_R
83 #ifdef CONFIG_MPC8349ITX
84 /* The CF card interface on the back of the board */
85 #define CONFIG_COMPACT_FLASH
86 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
87 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
88 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
92 #define CONFIG_RTC_DS1337
93 #define CONFIG_HARD_I2C
94 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
97 * Device configurations
101 #ifdef CONFIG_HARD_I2C
103 #define CONFIG_FSL_I2C
104 #define CONFIG_I2C_MULTI_BUS
105 #define CONFIG_SYS_I2C_OFFSET 0x3000
106 #define CONFIG_SYS_I2C2_OFFSET 0x3100
107 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
108 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
110 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
111 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
112 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
113 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
114 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
115 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
116 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
118 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
119 #define CONFIG_SYS_I2C_SLAVE 0x7F
121 /* Don't probe these addresses: */
122 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
123 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
124 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
125 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
126 /* Bit definitions for the 8574[A] I2C expander */
127 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
128 #define I2C_8574_REVISION 0x03
129 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
130 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
131 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
132 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
134 #undef CONFIG_SOFT_I2C
139 #ifdef CONFIG_COMPACT_FLASH
141 #define CONFIG_SYS_IDE_MAXBUS 1
142 #define CONFIG_SYS_IDE_MAXDEVICE 1
144 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
145 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
146 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
147 #define CONFIG_SYS_ATA_REG_OFFSET 0
148 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
149 #define CONFIG_SYS_ATA_STRIDE 2
151 /* If a CF card is not inserted, time out quickly */
152 #define ATA_RESET_TIME 1
159 #ifdef CONFIG_SATA_SIL3114
161 #define CONFIG_SYS_SATA_MAX_DEVICE 4
162 #define CONFIG_LIBATA
167 #ifdef CONFIG_SYS_USB_HOST
171 #define CONFIG_CMD_USB
172 #define CONFIG_USB_STORAGE
173 #define CONFIG_USB_EHCI
174 #define CONFIG_USB_EHCI_FSL
176 /* Current USB implementation supports the only USB controller,
177 * so we have to choose between the MPH or the DR ones */
179 #define CONFIG_HAS_FSL_MPH_USB
181 #define CONFIG_HAS_FSL_DR_USB
189 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
191 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
192 #define CONFIG_SYS_83XX_DDR_USES_CS0
193 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
194 #define CONFIG_SYS_MEMTEST_END 0x2000
196 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
197 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
199 #define CONFIG_VERY_BIG_RAM
200 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
202 #ifdef CONFIG_HARD_I2C
203 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
206 /* No SPD? Then manually set up DDR parameters */
207 #ifndef CONFIG_SPD_EEPROM
208 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
209 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
210 | CSCONFIG_ROW_BIT_13 \
211 | CSCONFIG_COL_BIT_10)
213 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
214 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
218 *Flash on the Local Bus
221 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
222 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
223 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
224 #define CONFIG_SYS_FLASH_EMPTY_INFO
225 /* 127 64KB sectors + 8 8KB sectors per device */
226 #define CONFIG_SYS_MAX_FLASH_SECT 135
227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
229 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
231 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
232 boards, we say we have two, but don't display a message if we find only one. */
233 #define CONFIG_SYS_FLASH_QUIET_TEST
234 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
235 #define CONFIG_SYS_FLASH_BANKS_LIST \
236 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
237 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
238 #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
239 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
243 #ifdef CONFIG_VSC7385_ENET
247 /* The flash address and size of the VSC7385 firmware image */
248 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
249 #define CONFIG_VSC7385_IMAGE_SIZE 8192
254 * BRx, ORx, LBLAWBARx, and LBLAWARx
259 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
260 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
269 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
270 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
271 | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
275 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
277 #ifdef CONFIG_VSC7385_ENET
279 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
280 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
289 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
290 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
296 #define CONFIG_SYS_LED_BASE 0xF9000000
297 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
298 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
309 #ifdef CONFIG_COMPACT_FLASH
311 #define CONFIG_SYS_CF_BASE 0xF0000000
313 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
317 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
319 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
320 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
325 * U-Boot memory configuration
327 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
329 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
330 #define CONFIG_SYS_RAMBOOT
332 #undef CONFIG_SYS_RAMBOOT
335 #define CONFIG_SYS_INIT_RAM_LOCK
336 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
337 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
339 #define CONFIG_SYS_GBL_DATA_OFFSET \
340 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
341 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
343 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
344 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
345 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
348 * Local Bus LCRR and LBCR regs
349 * LCRR: DLL bypass, Clock divider is 4
350 * External Local Bus rate is
351 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
353 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
354 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
355 #define CONFIG_SYS_LBC_LBCR 0x00000000
357 /* LB sdram refresh timer, about 6us */
358 #define CONFIG_SYS_LBC_LSRT 0x32000000
359 /* LB refresh timer prescal, 266MHz/32*/
360 #define CONFIG_SYS_LBC_MRTPR 0x20000000
365 #define CONFIG_CONS_INDEX 1
366 #define CONFIG_SYS_NS16550
367 #define CONFIG_SYS_NS16550_SERIAL
368 #define CONFIG_SYS_NS16550_REG_SIZE 1
369 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
371 #define CONFIG_SYS_BAUDRATE_TABLE \
372 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
374 #define CONFIG_CONSOLE ttyS0
375 #define CONFIG_BAUDRATE 115200
377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
380 /* pass open firmware flat tree */
381 #define CONFIG_OF_LIBFDT 1
382 #define CONFIG_OF_BOARD_SETUP 1
383 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
390 #define CONFIG_MPC83XX_PCI2
394 * Addresses are mapped 1-1.
396 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
397 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
398 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
399 #define CONFIG_SYS_PCI1_MMIO_BASE \
400 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
401 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
402 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
403 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
404 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
405 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
407 #ifdef CONFIG_MPC83XX_PCI2
408 #define CONFIG_SYS_PCI2_MEM_BASE \
409 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
410 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
411 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
412 #define CONFIG_SYS_PCI2_MMIO_BASE \
413 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
414 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
415 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
416 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
417 #define CONFIG_SYS_PCI2_IO_PHYS \
418 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
419 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
422 #define CONFIG_PCI_PNP /* do pci plug-and-play */
424 #ifndef CONFIG_PCI_PNP
425 #define PCI_ENET0_IOADDR 0x00000000
426 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
427 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
430 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
434 #define CONFIG_PCI_66M
435 #ifdef CONFIG_PCI_66M
436 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */
438 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
443 #ifdef CONFIG_TSEC_ENET
446 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
451 #define CONFIG_HAS_ETH0
452 #define CONFIG_TSEC1_NAME "TSEC0"
453 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
454 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
455 #define TSEC1_PHYIDX 0
456 #define TSEC1_FLAGS TSEC_GIGABIT
460 #define CONFIG_HAS_ETH1
461 #define CONFIG_TSEC2_NAME "TSEC1"
462 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
464 #define TSEC2_PHY_ADDR 4
465 #define TSEC2_PHYIDX 0
466 #define TSEC2_FLAGS TSEC_GIGABIT
469 #define CONFIG_ETHPRIME "Freescale TSEC"
476 #define CONFIG_ENV_OVERWRITE
478 #ifndef CONFIG_SYS_RAMBOOT
479 #define CONFIG_ENV_IS_IN_FLASH
480 #define CONFIG_ENV_ADDR \
481 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
482 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
483 #define CONFIG_ENV_SIZE 0x2000
485 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
486 #undef CONFIG_FLASH_CFI_DRIVER
487 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
488 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
489 #define CONFIG_ENV_SIZE 0x2000
492 #define CONFIG_LOADS_ECHO /* echo on for serial download */
493 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
498 #define CONFIG_BOOTP_BOOTFILESIZE
499 #define CONFIG_BOOTP_BOOTPATH
500 #define CONFIG_BOOTP_GATEWAY
501 #define CONFIG_BOOTP_HOSTNAME
505 * Command line configuration.
507 #include <config_cmd_default.h>
509 #define CONFIG_CMD_CACHE
510 #define CONFIG_CMD_DATE
511 #define CONFIG_CMD_IRQ
512 #define CONFIG_CMD_NET
513 #define CONFIG_CMD_PING
514 #define CONFIG_CMD_DHCP
515 #define CONFIG_CMD_SDRAM
517 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
518 || defined(CONFIG_USB_STORAGE)
519 #define CONFIG_DOS_PARTITION
520 #define CONFIG_CMD_FAT
521 #define CONFIG_SUPPORT_VFAT
524 #ifdef CONFIG_COMPACT_FLASH
525 #define CONFIG_CMD_IDE
528 #ifdef CONFIG_SATA_SIL3114
529 #define CONFIG_CMD_SATA
532 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
533 #define CONFIG_CMD_EXT2
537 #define CONFIG_CMD_PCI
540 #ifdef CONFIG_HARD_I2C
541 #define CONFIG_CMD_I2C
545 #undef CONFIG_WATCHDOG /* watchdog disabled */
548 * Miscellaneous configurable options
550 #define CONFIG_SYS_LONGHELP /* undef to save memory */
551 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
552 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
553 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
554 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
556 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
557 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
559 #ifdef CONFIG_MPC8349ITX
560 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
562 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
565 #if defined(CONFIG_CMD_KGDB)
566 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
568 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
571 /* Print Buffer Size */
572 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
573 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
574 /* Boot Argument Buffer Size */
575 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
576 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
579 * For booting Linux, the board info and command line data
580 * have to be in the first 256 MB of memory, since this is
581 * the maximum mapped by the Linux kernel during initialization.
583 /* Initial Memory map for Linux*/
584 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
586 #define CONFIG_SYS_HRCW_LOW (\
587 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
588 HRCWL_DDR_TO_SCB_CLK_1X1 |\
589 HRCWL_CSB_TO_CLKIN_4X1 |\
591 HRCWL_CORE_TO_CSB_2X1)
593 #ifdef CONFIG_SYS_LOWBOOT
594 #define CONFIG_SYS_HRCW_HIGH (\
597 HRCWH_PCI1_ARBITER_ENABLE |\
598 HRCWH_PCI2_ARBITER_ENABLE |\
600 HRCWH_FROM_0X00000100 |\
601 HRCWH_BOOTSEQ_DISABLE |\
602 HRCWH_SW_WATCHDOG_DISABLE |\
603 HRCWH_ROM_LOC_LOCAL_16BIT |\
604 HRCWH_TSEC1M_IN_GMII |\
605 HRCWH_TSEC2M_IN_GMII)
607 #define CONFIG_SYS_HRCW_HIGH (\
610 HRCWH_PCI1_ARBITER_ENABLE |\
611 HRCWH_PCI2_ARBITER_ENABLE |\
613 HRCWH_FROM_0XFFF00100 |\
614 HRCWH_BOOTSEQ_DISABLE |\
615 HRCWH_SW_WATCHDOG_DISABLE |\
616 HRCWH_ROM_LOC_LOCAL_16BIT |\
617 HRCWH_TSEC1M_IN_GMII |\
618 HRCWH_TSEC2M_IN_GMII)
624 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
625 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
626 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
627 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
628 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
629 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
630 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
631 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
636 /* Needed for gigabit to work on TSEC 1 */
637 #define CONFIG_SYS_SICRH SICRH_TSOBI1
638 /* USB DR as device + USB MPH as host */
639 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
641 #define CONFIG_SYS_HID0_INIT 0x00000000
642 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
644 #define CONFIG_SYS_HID2 HID2_HBE
645 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
648 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
651 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
658 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
661 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
665 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
667 | BATL_CACHEINHIBIT \
668 | BATL_GUARDEDSTORAGE)
669 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
674 #define CONFIG_SYS_IBAT1L 0
675 #define CONFIG_SYS_IBAT1U 0
676 #define CONFIG_SYS_IBAT2L 0
677 #define CONFIG_SYS_IBAT2U 0
680 #ifdef CONFIG_MPC83XX_PCI2
681 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
684 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
688 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
690 | BATL_CACHEINHIBIT \
691 | BATL_GUARDEDSTORAGE)
692 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
697 #define CONFIG_SYS_IBAT3L 0
698 #define CONFIG_SYS_IBAT3U 0
699 #define CONFIG_SYS_IBAT4L 0
700 #define CONFIG_SYS_IBAT4U 0
703 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
704 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
706 | BATL_CACHEINHIBIT \
707 | BATL_GUARDEDSTORAGE)
708 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
713 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
714 #define CONFIG_SYS_IBAT6L (0xF0000000 \
716 | BATL_MEMCOHERENCE \
717 | BATL_GUARDEDSTORAGE)
718 #define CONFIG_SYS_IBAT6U (0xF0000000 \
723 #define CONFIG_SYS_IBAT7L 0
724 #define CONFIG_SYS_IBAT7U 0
726 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
727 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
728 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
729 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
730 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
731 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
732 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
733 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
734 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
735 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
736 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
737 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
738 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
739 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
740 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
741 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
743 #if defined(CONFIG_CMD_KGDB)
744 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
745 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
750 * Environment Configuration
752 #define CONFIG_ENV_OVERWRITE
754 #define CONFIG_NETDEV "eth0"
756 #ifdef CONFIG_MPC8349ITX
757 #define CONFIG_HOSTNAME "mpc8349emitx"
759 #define CONFIG_HOSTNAME "mpc8349emitxgp"
762 /* Default path and filenames */
763 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
764 #define CONFIG_BOOTFILE "uImage"
765 /* U-Boot image on TFTP server */
766 #define CONFIG_UBOOTPATH "u-boot.bin"
768 #ifdef CONFIG_MPC8349ITX
769 #define CONFIG_FDTFILE "mpc8349emitx.dtb"
771 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
774 #define CONFIG_BOOTDELAY 6
776 #define XMK_STR(x) #x
777 #define MK_STR(x) XMK_STR(x)
779 #define CONFIG_BOOTARGS \
781 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
782 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
783 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
784 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
785 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
787 #define CONFIG_EXTRA_ENV_SETTINGS \
788 "console=" MK_STR(CONFIG_CONSOLE) "\0" \
789 "netdev=" CONFIG_NETDEV "\0" \
790 "uboot=" CONFIG_UBOOTPATH "\0" \
791 "tftpflash=tftpboot $loadaddr $uboot; " \
792 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
793 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
794 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
795 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
796 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
798 "fdtfile=" CONFIG_FDTFILE "\0"
800 #define CONFIG_NFSBOOTCOMMAND \
801 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
802 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
803 " console=$console,$baudrate $othbootargs; " \
804 "tftp $loadaddr $bootfile;" \
805 "tftp $fdtaddr $fdtfile;" \
806 "bootm $loadaddr - $fdtaddr"
808 #define CONFIG_RAMBOOTCOMMAND \
809 "setenv bootargs root=/dev/ram rw" \
810 " console=$console,$baudrate $othbootargs; " \
811 "tftp $ramdiskaddr $ramdiskfile;" \
812 "tftp $loadaddr $bootfile;" \
813 "tftp $fdtaddr $fdtfile;" \
814 "bootm $loadaddr $ramdiskaddr $fdtaddr"