2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * High Level Configuration Options
28 #define CONFIG_E300 1 /* E300 family */
29 #define CONFIG_QE 1 /* Has QE */
30 #define CONFIG_MPC83xx 1 /* MPC83xx family */
31 #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
32 #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
34 #define CONFIG_SYS_TEXT_BASE 0xFE000000
36 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
37 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
42 #ifdef CONFIG_PCISLAVE
43 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
45 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
48 #ifndef CONFIG_SYS_CLK_FREQ
49 #define CONFIG_SYS_CLK_FREQ 66000000
53 * Hardware Reset Configuration Word
55 #define CONFIG_SYS_HRCW_LOW (\
56 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
57 HRCWL_DDR_TO_SCB_CLK_1X1 |\
58 HRCWL_CSB_TO_CLKIN_4X1 |\
60 HRCWL_CE_PLL_VCO_DIV_4 |\
61 HRCWL_CE_PLL_DIV_1X1 |\
62 HRCWL_CE_TO_PLL_1X6 |\
63 HRCWL_CORE_TO_CSB_2X1)
65 #ifdef CONFIG_PCISLAVE
66 #define CONFIG_SYS_HRCW_HIGH (\
68 HRCWH_PCI1_ARBITER_DISABLE |\
69 HRCWH_PCICKDRV_DISABLE |\
71 HRCWH_FROM_0XFFF00100 |\
72 HRCWH_BOOTSEQ_DISABLE |\
73 HRCWH_SW_WATCHDOG_DISABLE |\
74 HRCWH_ROM_LOC_LOCAL_16BIT)
76 #define CONFIG_SYS_HRCW_HIGH (\
78 HRCWH_PCI1_ARBITER_ENABLE |\
79 HRCWH_PCICKDRV_ENABLE |\
81 HRCWH_FROM_0X00000100 |\
82 HRCWH_BOOTSEQ_DISABLE |\
83 HRCWH_SW_WATCHDOG_DISABLE |\
84 HRCWH_ROM_LOC_LOCAL_16BIT)
90 #define CONFIG_SYS_SICRH 0x00000000
91 #define CONFIG_SYS_SICRL 0x40000000
93 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
94 #define CONFIG_BOARD_EARLY_INIT_R
99 #define CONFIG_SYS_IMMR 0xE0000000
104 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
106 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
107 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
108 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
109 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
111 #define CONFIG_SYS_83XX_DDR_USES_CS0
113 #define CONFIG_DDR_ECC /* support DDR ECC function */
114 #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
117 * DDRCDR - DDR Control Driver Register
119 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
121 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
122 #if defined(CONFIG_SPD_EEPROM)
124 * Determine DDR configuration from I2C interface.
126 #define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
129 * Manually set up DDR parameters
131 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
132 #if defined(CONFIG_DDR_II)
133 #define CONFIG_SYS_DDRCDR 0x80080001
134 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
136 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
137 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
138 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
140 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
141 #define CONFIG_SYS_DDR_MODE 0x47d00432
142 #define CONFIG_SYS_DDR_MODE2 0x8000c000
143 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
144 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
145 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
147 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
148 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
149 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
150 #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
151 #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
152 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
159 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
160 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
161 #define CONFIG_SYS_MEMTEST_END 0x00100000
164 * The reserved memory
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
169 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
170 #define CONFIG_SYS_RAMBOOT
172 #undef CONFIG_SYS_RAMBOOT
175 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
176 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
177 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
180 * Initial RAM Base Address Setup
182 #define CONFIG_SYS_INIT_RAM_LOCK 1
183 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
184 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
188 * Local Bus Configuration & Clock Setup
190 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
191 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
192 #define CONFIG_SYS_LBC_LBCR 0x00000000
195 * FLASH on the Local Bus
197 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
198 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
199 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
200 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
201 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
202 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
204 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
205 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
207 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
208 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
210 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
211 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
212 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
215 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
217 #undef CONFIG_SYS_FLASH_CHECKSUM
220 * BCSR on the Local Bus
222 #define CONFIG_SYS_BCSR 0xF8000000
223 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
224 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
226 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
227 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
230 * SDRAM on the Local Bus
232 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
233 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
235 #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
237 #ifdef CONFIG_SYS_LB_SDRAM
238 #define CONFIG_SYS_LBLAWBAR2 0
239 #define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */
241 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
243 * Base Register 2 and Option Register 2 configure SDRAM.
246 * Base address = BR[0:16] = dynamic
247 * port size = 32-bits = BR2[19:20] = 11
248 * no parity checking = BR2[21:22] = 00
249 * SDRAM for MSEL = BR2[24:26] = 011
252 * 0 4 8 12 16 20 24 28
253 * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
256 #define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */
259 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
262 * 64MB mask for AM, OR2[0:7] = 1111 1100
263 * XAM, OR2[17:18] = 11
264 * 9 columns OR2[19-21] = 010
265 * 13 rows OR2[23-25] = 100
266 * EAD set for extra time OR[31] = 1
268 * 0 4 8 12 16 20 24 28
269 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
272 #define CONFIG_SYS_OR2 0xfc006901
274 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
275 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
277 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
280 * SDRAM Controller configuration sequence.
282 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
283 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
284 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
285 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
286 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
291 * Windows to access PIB via local bus
293 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
294 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
297 * CS4 on Local Bus, to PIB
299 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
300 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
303 * CS5 on Local Bus, to PIB
305 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
306 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
311 #define CONFIG_CONS_INDEX 1
312 #define CONFIG_SYS_NS16550
313 #define CONFIG_SYS_NS16550_SERIAL
314 #define CONFIG_SYS_NS16550_REG_SIZE 1
315 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
317 #define CONFIG_SYS_BAUDRATE_TABLE \
318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
323 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
324 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
325 /* Use the HUSH parser */
326 #define CONFIG_SYS_HUSH_PARSER
327 #ifdef CONFIG_SYS_HUSH_PARSER
328 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
331 /* pass open firmware flat tree */
332 #define CONFIG_OF_LIBFDT 1
333 #define CONFIG_OF_BOARD_SETUP 1
334 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
337 #define CONFIG_HARD_I2C /* I2C with hardware support */
338 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
339 #define CONFIG_FSL_I2C
340 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
341 #define CONFIG_SYS_I2C_SLAVE 0x7F
342 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
343 #define CONFIG_SYS_I2C_OFFSET 0x3000
344 #define CONFIG_SYS_I2C2_OFFSET 0x3100
347 * Config on-board RTC
349 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
350 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
354 * Addresses are mapped 1-1.
356 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
357 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
358 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
359 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
360 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
361 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
362 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
363 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
364 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
366 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
367 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
368 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
373 #define CONFIG_PCI_PNP /* do pci plug-and-play */
374 #define CONFIG_83XX_PCI_STREAMING
376 #undef CONFIG_EEPRO100
377 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
380 #endif /* CONFIG_PCI */
383 #define CONFIG_HWCONFIG 1
386 * QE UEC ethernet configuration
388 #define CONFIG_UEC_ETH
389 #define CONFIG_ETHPRIME "UEC0"
390 #define CONFIG_PHY_MODE_NEED_CHANGE
392 #define CONFIG_UEC_ETH1 /* GETH1 */
394 #ifdef CONFIG_UEC_ETH1
395 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
396 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
397 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
398 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
399 #define CONFIG_SYS_UEC1_PHY_ADDR 0
400 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
401 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
404 #define CONFIG_UEC_ETH2 /* GETH2 */
406 #ifdef CONFIG_UEC_ETH2
407 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
408 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
409 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
410 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
411 #define CONFIG_SYS_UEC2_PHY_ADDR 1
412 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
413 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
420 #ifndef CONFIG_SYS_RAMBOOT
421 #define CONFIG_ENV_IS_IN_FLASH 1
422 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
423 #define CONFIG_ENV_SECT_SIZE 0x20000
424 #define CONFIG_ENV_SIZE 0x2000
426 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
427 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
429 #define CONFIG_ENV_SIZE 0x2000
432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
433 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
438 #define CONFIG_BOOTP_BOOTFILESIZE
439 #define CONFIG_BOOTP_BOOTPATH
440 #define CONFIG_BOOTP_GATEWAY
441 #define CONFIG_BOOTP_HOSTNAME
445 * Command line configuration.
447 #include <config_cmd_default.h>
449 #define CONFIG_CMD_PING
450 #define CONFIG_CMD_I2C
451 #define CONFIG_CMD_ASKENV
452 #define CONFIG_CMD_SDRAM
454 #if defined(CONFIG_PCI)
455 #define CONFIG_CMD_PCI
458 #if defined(CONFIG_SYS_RAMBOOT)
459 #undef CONFIG_CMD_SAVEENV
460 #undef CONFIG_CMD_LOADS
464 #undef CONFIG_WATCHDOG /* watchdog disabled */
467 * Miscellaneous configurable options
469 #define CONFIG_SYS_LONGHELP /* undef to save memory */
470 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
471 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
473 #if defined(CONFIG_CMD_KGDB)
474 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
476 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
479 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
480 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
481 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
482 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
485 * For booting Linux, the board info and command line data
486 * have to be in the first 256 MB of memory, since this is
487 * the maximum mapped by the Linux kernel during initialization.
489 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
494 #define CONFIG_SYS_HID0_INIT 0x000000000
495 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
496 HID0_ENABLE_INSTRUCTION_CACHE)
497 #define CONFIG_SYS_HID2 HID2_HBE
503 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
505 /* DDR/LBC SDRAM: cacheable */
506 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
507 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
508 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
509 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
511 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
512 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
513 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
515 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
516 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
518 /* BCSR: cache-inhibit and guarded */
519 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
520 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
521 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
522 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
523 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
525 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
526 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
527 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
528 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
529 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
532 /* DDR/LBC SDRAM next 256M: cacheable */
533 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
534 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
535 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
536 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
538 /* Stack in dcache: cacheable, no memory coherence */
539 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
540 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
541 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
542 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
545 /* PCI MEM space: cacheable */
546 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
547 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
548 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
549 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
550 /* PCI MMIO space: cache-inhibit and guarded */
551 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
552 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
553 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
554 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
555 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
557 #define CONFIG_SYS_IBAT6L (0)
558 #define CONFIG_SYS_IBAT6U (0)
559 #define CONFIG_SYS_IBAT7L (0)
560 #define CONFIG_SYS_IBAT7U (0)
561 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
562 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
563 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
564 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
567 #if defined(CONFIG_CMD_KGDB)
568 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
569 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
573 * Environment Configuration
576 #define CONFIG_ENV_OVERWRITE
578 #if defined(CONFIG_UEC_ETH)
579 #define CONFIG_HAS_ETH0
580 #define CONFIG_HAS_ETH1
583 #define CONFIG_BAUDRATE 115200
585 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
587 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
588 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
590 #define CONFIG_EXTRA_ENV_SETTINGS \
592 "consoledev=ttyS0\0" \
593 "ramdiskaddr=1000000\0" \
594 "ramdiskfile=ramfs.83xx\0" \
596 "fdtfile=mpc836x_mds.dtb\0" \
599 #define CONFIG_NFSBOOTCOMMAND \
600 "setenv bootargs root=/dev/nfs rw " \
601 "nfsroot=$serverip:$rootpath " \
602 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr - $fdtaddr"
608 #define CONFIG_RAMBOOTCOMMAND \
609 "setenv bootargs root=/dev/ram rw " \
610 "console=$consoledev,$baudrate $othbootargs;" \
611 "tftp $ramdiskaddr $ramdiskfile;" \
612 "tftp $loadaddr $bootfile;" \
613 "tftp $fdtaddr $fdtfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr"
617 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
619 #endif /* __CONFIG_H */