git.sur5r.net Git - u-boot/blob - include/configs/MPC837XEMDS.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 /*
  25  * High Level Configuration Options
  26  */
  27 #define CONFIG_E300             1 /* E300 family */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
  30 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #ifdef CONFIG_PCISLAVE
  38 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  39 #else
  40 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #endif
  46
  47 /*
  48  * Hardware Reset Configuration Word
  49  * if CLKIN is 66MHz, then
  50  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  51  */
  52 #define CONFIG_SYS_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  55         HRCWL_SVCOD_DIV_2 |\
  56         HRCWL_CSB_TO_CLKIN_6X1 |\
  57         HRCWL_CORE_TO_CSB_1_5X1)
  58
  59 #ifdef CONFIG_PCISLAVE
  60 #define CONFIG_SYS_HRCW_HIGH (\
  61         HRCWH_PCI_AGENT |\
  62         HRCWH_PCI1_ARBITER_DISABLE |\
  63         HRCWH_CORE_ENABLE |\
  64         HRCWH_FROM_0XFFF00100 |\
  65         HRCWH_BOOTSEQ_DISABLE |\
  66         HRCWH_SW_WATCHDOG_DISABLE |\
  67         HRCWH_ROM_LOC_LOCAL_16BIT |\
  68         HRCWH_RL_EXT_LEGACY |\
  69         HRCWH_TSEC1M_IN_RGMII |\
  70         HRCWH_TSEC2M_IN_RGMII |\
  71         HRCWH_BIG_ENDIAN |\
  72         HRCWH_LDP_CLEAR)
  73 #else
  74 #define CONFIG_SYS_HRCW_HIGH (\
  75         HRCWH_PCI_HOST |\
  76         HRCWH_PCI1_ARBITER_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT |\
  82         HRCWH_RL_EXT_LEGACY |\
  83         HRCWH_TSEC1M_IN_RGMII |\
  84         HRCWH_TSEC2M_IN_RGMII |\
  85         HRCWH_BIG_ENDIAN |\
  86         HRCWH_LDP_CLEAR)
  87 #endif
  88
  89 /* Arbiter Configuration Register */
  90 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  91 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
  92
  93 /* System Priority Control Register */
  94 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
  95
  96 /*
  97  * IP blocks clock configuration
  98  */
  99 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
 100 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
 101 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
 102
 103 /*
 104  * System IO Config
 105  */
 106 #define CONFIG_SYS_SICRH                0x00000000
 107 #define CONFIG_SYS_SICRL                0x00000000
 108
 109 /*
 110  * Output Buffer Impedance
 111  */
 112 #define CONFIG_SYS_OBIR         0x31100000
 113
 114 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 115 #define CONFIG_BOARD_EARLY_INIT_R
 116 #define CONFIG_HWCONFIG
 117
 118 /*
 119  * IMMR new address
 120  */
 121 #define CONFIG_SYS_IMMR         0xE0000000
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 127 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 128 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 129 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 130 #define CONFIG_SYS_83XX_DDR_USES_CS0
 131 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
 132
 133 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 134 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 135
 136 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 137 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 138
 139 #if defined(CONFIG_SPD_EEPROM)
 140 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 141 #else
 142 /*
 143  * Manually set up DDR parameters
 144  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 145  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 146  */
 147 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
 148 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
 149 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 150                                 | 0x00010000  /* ODT_WR to CSn */ \
 151                                 | CSCONFIG_ROW_BIT_14 \
 152                                 | CSCONFIG_COL_BIT_10)
 153                                 /* 0x80010202 */
 154 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 155 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 156                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 157                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 158                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 159                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 160                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 161                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 162                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 163                                 /* 0x00620802 */
 164 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 165                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 166                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 167                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 168                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 169                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 170                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 171                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 172                                 /* 0x3935d322 */
 173 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 174                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
 175                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 176                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 177                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 178                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 179                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 180                                 /* 0x131088c8 */
 181 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
 182                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 183                                 /* 0x03E00100 */
 184 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 185 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 186 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 187                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
 188                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 189 #define CONFIG_SYS_DDR_MODE2    0x00000000
 190 #endif
 191
 192 /*
 193  * Memory test
 194  */
 195 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 196 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 197 #define CONFIG_SYS_MEMTEST_END          0x00140000
 198
 199 /*
 200  * The reserved memory
 201  */
 202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 203
 204 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 205 #define CONFIG_SYS_RAMBOOT
 206 #else
 207 #undef CONFIG_SYS_RAMBOOT
 208 #endif
 209
 210 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 211 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 212 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 213
 214 /*
 215  * Initial RAM Base Address Setup
 216  */
 217 #define CONFIG_SYS_INIT_RAM_LOCK        1
 218 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 219 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 220 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 221                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 222
 223 /*
 224  * Local Bus Configuration & Clock Setup
 225  */
 226 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 227 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 228 #define CONFIG_SYS_LBC_LBCR             0x00000000
 229 #define CONFIG_FSL_ELBC         1
 230
 231 /*
 232  * FLASH on the Local Bus
 233  */
 234 #define CONFIG_SYS_FLASH_CFI    /* use the Common Flash Interface */
 235 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 236 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 237 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 238 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 239
 240                                         /* Window base at flash base */
 241 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 242 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 243
 244 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 245                                 | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
 246                                 | BR_V)                 /* valid */
 247 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 248                                 | OR_UPM_XAM \
 249                                 | OR_GPCM_CSNT \
 250                                 | OR_GPCM_ACS_DIV2 \
 251                                 | OR_GPCM_XACS \
 252                                 | OR_GPCM_SCY_15 \
 253                                 | OR_GPCM_TRLX \
 254                                 | OR_GPCM_EHTR \
 255                                 | OR_GPCM_EAD)
 256                                 /* 0xFE000FF7 */
 257
 258 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 259 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 260
 261 #undef CONFIG_SYS_FLASH_CHECKSUM
 262 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 263 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 264
 265 /*
 266  * BCSR on the Local Bus
 267  */
 268 #define CONFIG_SYS_BCSR         0xF8000000
 269                                         /* Access window base at BCSR base */
 270 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 271 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E /* Access window size 32K */
 272
 273                                 /* Port size=8bit, MSEL=GPCM */
 274 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR | 0x00000801)
 275 #define CONFIG_SYS_OR1_PRELIM   0xFFFFE9f7 /* length 32K */
 276
 277 /*
 278  * NAND Flash on the Local Bus
 279  */
 280 #define CONFIG_CMD_NAND         1
 281 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 282 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 283 #define CONFIG_NAND_FSL_ELBC    1
 284
 285 #define CONFIG_SYS_NAND_BASE    0xE0600000      /* 0xE0600000 */
 286 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE \
 287                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 288                                 | BR_PS_8               /* 8 bit port */ \
 289                                 | BR_MS_FCM             /* MSEL = FCM */ \
 290                                 | BR_V)         /* valid */
 291 #define CONFIG_SYS_OR3_PRELIM   (0xFFFF8000     /* length 32K */ \
 292                                 | OR_FCM_BCTLD \
 293                                 | OR_FCM_CST \
 294                                 | OR_FCM_CHT \
 295                                 | OR_FCM_SCY_1 \
 296                                 | OR_FCM_RST \
 297                                 | OR_FCM_TRLX \
 298                                 | OR_FCM_EHTR)
 299                                 /* 0xFFFF919E */
 300
 301 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
 302 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E      /* 32KB  */
 303
 304 /*
 305  * Serial Port
 306  */
 307 #define CONFIG_CONS_INDEX       1
 308 #define CONFIG_SYS_NS16550
 309 #define CONFIG_SYS_NS16550_SERIAL
 310 #define CONFIG_SYS_NS16550_REG_SIZE     1
 311 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 312
 313 #define CONFIG_SYS_BAUDRATE_TABLE  \
 314                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 315
 316 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 317 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 318
 319 /* Use the HUSH parser */
 320 #define CONFIG_SYS_HUSH_PARSER
 321 #ifdef CONFIG_SYS_HUSH_PARSER
 322 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 323 #endif
 324
 325 /* Pass open firmware flat tree */
 326 #define CONFIG_OF_LIBFDT        1
 327 #define CONFIG_OF_BOARD_SETUP   1
 328 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 329
 330 /* I2C */
 331 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 332 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 333 #define CONFIG_FSL_I2C
 334 #define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
 335 #define CONFIG_SYS_I2C_SLAVE    0x7F
 336 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
 337 #define CONFIG_SYS_I2C_OFFSET   0x3000
 338 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 339
 340 /*
 341  * Config on-board RTC
 342  */
 343 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 344 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 345
 346 /*
 347  * General PCI
 348  * Addresses are mapped 1-1.
 349  */
 350 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 351 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 352 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 353 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 354 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 355 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 356 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 357 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 358 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 359
 360 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 361 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 362 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 363
 364 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 365 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 366 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 367 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 368 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 369 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 370 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 371 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 372 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 373
 374 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 375 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 376 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 377 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 378 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 379 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 380 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 381 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 382 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 383
 384 #ifdef CONFIG_PCI
 385 #ifndef __ASSEMBLY__
 386 extern int board_pci_host_broken(void);
 387 #endif
 388 #define CONFIG_PCIE
 389 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 390
 391 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 392
 393 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 394
 395 #undef CONFIG_EEPRO100
 396 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 398 #endif /* CONFIG_PCI */
 399
 400 /*
 401  * TSEC
 402  */
 403 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 404 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 405 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 406 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 407 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 408
 409 /*
 410  * TSEC ethernet configuration
 411  */
 412 #define CONFIG_MII              1 /* MII PHY management */
 413 #define CONFIG_TSEC1            1
 414 #define CONFIG_TSEC1_NAME       "eTSEC0"
 415 #define CONFIG_TSEC2            1
 416 #define CONFIG_TSEC2_NAME       "eTSEC1"
 417 #define TSEC1_PHY_ADDR          2
 418 #define TSEC2_PHY_ADDR          3
 419 #define TSEC1_PHY_ADDR_SGMII    8
 420 #define TSEC2_PHY_ADDR_SGMII    4
 421 #define TSEC1_PHYIDX            0
 422 #define TSEC2_PHYIDX            0
 423 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 424 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 425
 426 /* Options are: TSEC[0-1] */
 427 #define CONFIG_ETHPRIME         "eTSEC1"
 428
 429 /* SERDES */
 430 #define CONFIG_FSL_SERDES
 431 #define CONFIG_FSL_SERDES1      0xe3000
 432 #define CONFIG_FSL_SERDES2      0xe3100
 433
 434 /*
 435  * SATA
 436  */
 437 #define CONFIG_LIBATA
 438 #define CONFIG_FSL_SATA
 439
 440 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 441 #define CONFIG_SATA1
 442 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 443 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 444 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 445 #define CONFIG_SATA2
 446 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 447 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 448 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 449
 450 #ifdef CONFIG_FSL_SATA
 451 #define CONFIG_LBA48
 452 #define CONFIG_CMD_SATA
 453 #define CONFIG_DOS_PARTITION
 454 #define CONFIG_CMD_EXT2
 455 #endif
 456
 457 /*
 458  * Environment
 459  */
 460 #ifndef CONFIG_SYS_RAMBOOT
 461         #define CONFIG_ENV_IS_IN_FLASH  1
 462         #define CONFIG_ENV_ADDR         \
 463                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 464         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 465         #define CONFIG_ENV_SIZE         0x2000
 466 #else
 467         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 468         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 469         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 470         #define CONFIG_ENV_SIZE         0x2000
 471 #endif
 472
 473 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 474 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 475
 476 /*
 477  * BOOTP options
 478  */
 479 #define CONFIG_BOOTP_BOOTFILESIZE
 480 #define CONFIG_BOOTP_BOOTPATH
 481 #define CONFIG_BOOTP_GATEWAY
 482 #define CONFIG_BOOTP_HOSTNAME
 483
 484
 485 /*
 486  * Command line configuration.
 487  */
 488 #include <config_cmd_default.h>
 489
 490 #define CONFIG_CMD_PING
 491 #define CONFIG_CMD_I2C
 492 #define CONFIG_CMD_MII
 493 #define CONFIG_CMD_DATE
 494
 495 #if defined(CONFIG_PCI)
 496     #define CONFIG_CMD_PCI
 497 #endif
 498
 499 #if defined(CONFIG_SYS_RAMBOOT)
 500     #undef CONFIG_CMD_SAVEENV
 501     #undef CONFIG_CMD_LOADS
 502 #endif
 503
 504 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 505 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 506
 507 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 508
 509 #define CONFIG_MMC     1
 510
 511 #ifdef CONFIG_MMC
 512 #define CONFIG_FSL_ESDHC
 513 #define CONFIG_FSL_ESDHC_PIN_MUX
 514 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 515 #define CONFIG_CMD_MMC
 516 #define CONFIG_GENERIC_MMC
 517 #define CONFIG_CMD_EXT2
 518 #define CONFIG_CMD_FAT
 519 #define CONFIG_DOS_PARTITION
 520 #endif
 521
 522 /*
 523  * Miscellaneous configurable options
 524  */
 525 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 526 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 527 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 528
 529 #if defined(CONFIG_CMD_KGDB)
 530         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 531 #else
 532         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 533 #endif
 534
 535                                 /* Print Buffer Size */
 536 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 537 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 538                                 /* Boot Argument Buffer Size */
 539 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 540 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 541
 542 /*
 543  * For booting Linux, the board info and command line data
 544  * have to be in the first 256 MB of memory, since this is
 545  * the maximum mapped by the Linux kernel during initialization.
 546  */
 547 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 548
 549 /*
 550  * Core HID Setup
 551  */
 552 #define CONFIG_SYS_HID0_INIT    0x000000000
 553 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 554                                  HID0_ENABLE_INSTRUCTION_CACHE)
 555 #define CONFIG_SYS_HID2         HID2_HBE
 556
 557 /*
 558  * MMU Setup
 559  */
 560 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 561
 562 /* DDR: cache cacheable */
 563 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 564 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 565
 566 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 567                                 | BATL_PP_10 \
 568                                 | BATL_MEMCOHERENCE)
 569 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 570                                 | BATU_BL_256M \
 571                                 | BATU_VS \
 572                                 | BATU_VP)
 573 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 574 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 575
 576 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 577                                 | BATL_PP_10 \
 578                                 | BATL_MEMCOHERENCE)
 579 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 580                                 | BATU_BL_256M \
 581                                 | BATU_VS \
 582                                 | BATU_VP)
 583 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 584 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 585
 586 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 587 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 588                                 | BATL_PP_10 \
 589                                 | BATL_CACHEINHIBIT \
 590                                 | BATL_GUARDEDSTORAGE)
 591 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 592                                 | BATU_BL_8M \
 593                                 | BATU_VS \
 594                                 | BATU_VP)
 595 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 596 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 597
 598 /* BCSR: cache-inhibit and guarded */
 599 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR \
 600                                 | BATL_PP_10 \
 601                                 | BATL_CACHEINHIBIT \
 602                                 | BATL_GUARDEDSTORAGE)
 603 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR \
 604                                 | BATU_BL_128K \
 605                                 | BATU_VS \
 606                                 | BATU_VP)
 607 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 608 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 609
 610 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 611 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 612                                 | BATL_PP_10 \
 613                                 | BATL_MEMCOHERENCE)
 614 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 615                                 | BATU_BL_32M \
 616                                 | BATU_VS \
 617                                 | BATU_VP)
 618 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 619                                 | BATL_PP_10 \
 620                                 | BATL_CACHEINHIBIT \
 621                                 | BATL_GUARDEDSTORAGE)
 622 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 623
 624 /* Stack in dcache: cacheable, no memory coherence */
 625 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 626 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 627                                 | BATU_BL_128K \
 628                                 | BATU_VS \
 629                                 | BATU_VP)
 630 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 631 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 632
 633 #ifdef CONFIG_PCI
 634 /* PCI MEM space: cacheable */
 635 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 636                                 | BATL_PP_10 \
 637                                 | BATL_MEMCOHERENCE)
 638 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 639                                 | BATU_BL_256M \
 640                                 | BATU_VS \
 641                                 | BATU_VP)
 642 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 643 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 644 /* PCI MMIO space: cache-inhibit and guarded */
 645 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 646                                 | BATL_PP_10 \
 647                                 | BATL_CACHEINHIBIT \
 648                                 | BATL_GUARDEDSTORAGE)
 649 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 650                                 | BATU_BL_256M \
 651                                 | BATU_VS \
 652                                 | BATU_VP)
 653 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 654 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 655 #else
 656 #define CONFIG_SYS_IBAT6L       (0)
 657 #define CONFIG_SYS_IBAT6U       (0)
 658 #define CONFIG_SYS_IBAT7L       (0)
 659 #define CONFIG_SYS_IBAT7U       (0)
 660 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 661 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 662 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 663 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 664 #endif
 665
 666 #if defined(CONFIG_CMD_KGDB)
 667 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 668 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 669 #endif
 670
 671 /*
 672  * Environment Configuration
 673  */
 674
 675 #define CONFIG_ENV_OVERWRITE
 676
 677 #if defined(CONFIG_TSEC_ENET)
 678 #define CONFIG_HAS_ETH0
 679 #define CONFIG_HAS_ETH1
 680 #endif
 681
 682 #define CONFIG_BAUDRATE 115200
 683
 684 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 685
 686 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 687 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 688
 689 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 690         "netdev=eth0\0"                                                 \
 691         "consoledev=ttyS0\0"                                            \
 692         "ramdiskaddr=1000000\0"                                         \
 693         "ramdiskfile=ramfs.83xx\0"                                      \
 694         "fdtaddr=780000\0"                                              \
 695         "fdtfile=mpc8379_mds.dtb\0"                                     \
 696         ""
 697
 698 #define CONFIG_NFSBOOTCOMMAND                                           \
 699         "setenv bootargs root=/dev/nfs rw "                             \
 700                 "nfsroot=$serverip:$rootpath "                          \
 701                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 702                                                         "$netdev:off "  \
 703                 "console=$consoledev,$baudrate $othbootargs;"           \
 704         "tftp $loadaddr $bootfile;"                                     \
 705         "tftp $fdtaddr $fdtfile;"                                       \
 706         "bootm $loadaddr - $fdtaddr"
 707
 708 #define CONFIG_RAMBOOTCOMMAND                                           \
 709         "setenv bootargs root=/dev/ram rw "                             \
 710                 "console=$consoledev,$baudrate $othbootargs;"           \
 711         "tftp $ramdiskaddr $ramdiskfile;"                               \
 712         "tftp $loadaddr $bootfile;"                                     \
 713         "tftp $fdtaddr $fdtfile;"                                       \
 714         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 715
 716
 717 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 718
 719 #endif  /* __CONFIG_H */