2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8569mds board configuration file
29 /* High Level Configuration Options */
30 #define CONFIG_BOOKE 1 /* BOOKE */
31 #define CONFIG_E500 1 /* BOOKE e500 family */
32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
33 #define CONFIG_MPC8569 1 /* MPC8569 specific */
34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
38 #define CONFIG_SYS_SRIO
39 #define CONFIG_SRIO1 /* SRIO port 1 */
41 #define CONFIG_PCI 1 /* Disable PCI/PCIE */
42 #define CONFIG_PCIE1 1 /* PCIE controller */
43 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
44 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47 #define CONFIG_QE /* Enable QE */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52 extern unsigned long get_clock_freq(void);
54 /* Replace a call to get_clock_freq (after it is implemented)*/
55 #define CONFIG_SYS_CLK_FREQ 66666666
56 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
59 #define CONFIG_PQ_MDS_PIB
60 #define CONFIG_PQ_MDS_PIB_ATM
64 * These can be toggled for performance analysis, otherwise use default.
66 #define CONFIG_L2_CACHE /* toggle L2 cache */
67 #define CONFIG_BTB /* toggle branch predition */
70 #define CONFIG_NAND_U_BOOT 1
71 #define CONFIG_RAMBOOT_NAND 1
72 #ifdef CONFIG_NAND_SPL
73 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
76 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
77 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
81 #ifndef CONFIG_SYS_TEXT_BASE
82 #define CONFIG_SYS_TEXT_BASE 0xfff80000
85 #ifndef CONFIG_SYS_MONITOR_BASE
86 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
90 * Only possible on E500 Version 2 or newer cores.
92 #define CONFIG_ENABLE_36BIT_PHYS 1
94 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
95 #define CONFIG_BOARD_EARLY_INIT_R 1
96 #define CONFIG_HWCONFIG
98 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
99 #define CONFIG_SYS_MEMTEST_END 0x00400000
102 * Config the L2 Cache as L2 SRAM
104 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
105 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
106 #define CONFIG_SYS_L2_SIZE (512 << 10)
107 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
109 #define CONFIG_SYS_CCSRBAR 0xe0000000
110 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
112 #if defined(CONFIG_NAND_SPL)
113 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
117 #define CONFIG_FSL_DDR3
118 #undef CONFIG_FSL_DDR_INTERACTIVE
119 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
120 #define CONFIG_DDR_SPD
121 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
123 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
125 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
126 /* DDR is system memory*/
127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
129 #define CONFIG_NUM_DDR_CONTROLLERS 1
130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
131 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
133 /* I2C addresses of SPD EEPROMs */
134 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
136 /* These are used when DDR doesn't use SPD. */
137 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
138 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
139 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
140 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
141 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
142 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
143 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
144 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
145 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
146 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
147 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
148 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
150 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
151 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
152 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
153 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
154 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
155 #define CONFIG_SYS_DDR_CDR_1 0x80040000
156 #define CONFIG_SYS_DDR_CDR_2 0x00000000
157 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
158 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
159 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
160 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
162 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
163 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
164 #define CONFIG_SYS_DDR_SBE 0x00010000
166 #undef CONFIG_CLOCKS_IN_MHZ
169 * Local Bus Definitions
172 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
175 #define CONFIG_SYS_BCSR_BASE 0xf8000000
176 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
178 /*Chip select 0 - Flash*/
179 #define CONFIG_FLASH_BR_PRELIM 0xfe000801
180 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
182 /*Chip select 1 - BCSR*/
183 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
184 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
186 /*Chip select 4 - PIB*/
187 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
188 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
190 /*Chip select 5 - PIB*/
191 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
192 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
194 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
195 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
196 #undef CONFIG_SYS_FLASH_CHECKSUM
197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
200 #if defined(CONFIG_RAMBOOT_NAND)
201 #define CONFIG_SYS_RAMBOOT
202 #define CONFIG_SYS_EXTRA_ENV_RELOC
204 #undef CONFIG_SYS_RAMBOOT
207 #define CONFIG_FLASH_CFI_DRIVER
208 #define CONFIG_SYS_FLASH_CFI
209 #define CONFIG_SYS_FLASH_EMPTY_INFO
211 /* Chip select 3 - NAND */
212 #ifndef CONFIG_NAND_SPL
213 #define CONFIG_SYS_NAND_BASE 0xFC000000
215 #define CONFIG_SYS_NAND_BASE 0xFFF00000
218 /* NAND boot: 4K NAND loader config */
219 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
220 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
221 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
222 #define CONFIG_SYS_NAND_U_BOOT_START \
223 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
224 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
225 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
226 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
228 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
229 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
230 #define CONFIG_SYS_MAX_NAND_DEVICE 1
231 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
232 #define CONFIG_CMD_NAND 1
233 #define CONFIG_NAND_FSL_ELBC 1
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
235 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
236 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
237 | BR_PS_8 /* Port Size = 8 bit */ \
238 | BR_MS_FCM /* MSEL = FCM */ \
240 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
248 #ifdef CONFIG_RAMBOOT_NAND
249 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
250 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
251 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
252 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
254 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
255 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
256 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
260 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
261 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
262 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
263 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
265 #define CONFIG_SYS_INIT_RAM_LOCK 1
266 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
267 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
269 #define CONFIG_SYS_GBL_DATA_OFFSET \
270 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
271 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
273 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
274 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
277 #define CONFIG_CONS_INDEX 1
278 #define CONFIG_SYS_NS16550
279 #define CONFIG_SYS_NS16550_SERIAL
280 #define CONFIG_SYS_NS16550_REG_SIZE 1
281 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
282 #ifdef CONFIG_NAND_SPL
283 #define CONFIG_NS16550_MIN_FUNCTIONS
286 #define CONFIG_SYS_BAUDRATE_TABLE \
287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
289 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
290 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
292 /* Use the HUSH parser*/
293 #define CONFIG_SYS_HUSH_PARSER
294 #ifdef CONFIG_SYS_HUSH_PARSER
297 /* pass open firmware flat tree */
298 #define CONFIG_OF_LIBFDT 1
299 #define CONFIG_OF_BOARD_SETUP 1
300 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
305 #define CONFIG_SYS_I2C
306 #define CONFIG_SYS_I2C_FSL
307 #define CONFIG_SYS_FSL_I2C_SPEED 400000
308 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
309 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
310 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
311 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
312 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
313 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
318 #define CONFIG_ID_EEPROM
319 #ifdef CONFIG_ID_EEPROM
320 #define CONFIG_SYS_I2C_EEPROM_NXID
322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
324 #define CONFIG_SYS_EEPROM_BUS_NUM 1
326 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
327 #define PLPPAR1_I2C2_VAL 0x00000000
328 #define PLPPAR1_ESDHC_VAL 0x0000000A
329 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
330 #define PLPDIR1_I2C2_VAL 0x0000000F
331 #define PLPDIR1_ESDHC_VAL 0x00000006
332 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
333 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
334 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
335 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
339 * Memory Addresses are mapped 1-1. I/O is mapped from 0
341 #define CONFIG_SYS_PCIE1_NAME "Slot"
342 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
343 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
344 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
345 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
346 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
347 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
348 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
349 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
351 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
352 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
353 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
354 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
358 * QE UEC ethernet configuration
360 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
361 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
363 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
364 #define CONFIG_UEC_ETH
365 #define CONFIG_ETHPRIME "UEC0"
366 #define CONFIG_PHY_MODE_NEED_CHANGE
368 #define CONFIG_UEC_ETH1 /* GETH1 */
369 #define CONFIG_HAS_ETH0
371 #ifdef CONFIG_UEC_ETH1
372 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
373 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
374 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
375 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
376 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
377 #define CONFIG_SYS_UEC1_PHY_ADDR 7
378 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
379 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
380 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
381 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
382 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
383 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
384 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
385 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
386 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
387 #endif /* CONFIG_UEC_ETH1 */
389 #define CONFIG_UEC_ETH2 /* GETH2 */
390 #define CONFIG_HAS_ETH1
392 #ifdef CONFIG_UEC_ETH2
393 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
394 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
395 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
396 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
397 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
398 #define CONFIG_SYS_UEC2_PHY_ADDR 1
399 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
400 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
401 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
402 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
403 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
404 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
405 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
406 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
407 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
408 #endif /* CONFIG_UEC_ETH2 */
410 #define CONFIG_UEC_ETH3 /* GETH3 */
411 #define CONFIG_HAS_ETH2
413 #ifdef CONFIG_UEC_ETH3
414 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
415 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
416 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
417 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
418 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
419 #define CONFIG_SYS_UEC3_PHY_ADDR 2
420 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
421 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
422 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
423 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
424 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
425 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
426 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
427 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
428 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
429 #endif /* CONFIG_UEC_ETH3 */
431 #define CONFIG_UEC_ETH4 /* GETH4 */
432 #define CONFIG_HAS_ETH3
434 #ifdef CONFIG_UEC_ETH4
435 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
436 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
437 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
438 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
439 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
440 #define CONFIG_SYS_UEC4_PHY_ADDR 3
441 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
442 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
443 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
444 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
445 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
446 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
447 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
448 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
449 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
450 #endif /* CONFIG_UEC_ETH4 */
452 #undef CONFIG_UEC_ETH6 /* GETH6 */
453 #define CONFIG_HAS_ETH5
455 #ifdef CONFIG_UEC_ETH6
456 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
457 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
458 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
459 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
460 #define CONFIG_SYS_UEC6_PHY_ADDR 4
461 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
462 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
463 #endif /* CONFIG_UEC_ETH6 */
465 #undef CONFIG_UEC_ETH8 /* GETH8 */
466 #define CONFIG_HAS_ETH7
468 #ifdef CONFIG_UEC_ETH8
469 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
470 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
471 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
472 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
473 #define CONFIG_SYS_UEC8_PHY_ADDR 6
474 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
475 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
476 #endif /* CONFIG_UEC_ETH8 */
478 #endif /* CONFIG_QE */
480 #if defined(CONFIG_PCI)
482 #define CONFIG_PCI_PNP /* do pci plug-and-play */
484 #undef CONFIG_EEPRO100
486 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
488 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
490 #endif /* CONFIG_PCI */
495 #if defined(CONFIG_SYS_RAMBOOT)
496 #if defined(CONFIG_RAMBOOT_NAND)
497 #define CONFIG_ENV_IS_IN_NAND 1
498 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
499 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
502 #define CONFIG_ENV_IS_IN_FLASH 1
503 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
504 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
505 #define CONFIG_ENV_SIZE 0x2000
508 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
509 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
511 /* QE microcode/firmware address */
512 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
513 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
518 #define CONFIG_BOOTP_BOOTFILESIZE
519 #define CONFIG_BOOTP_BOOTPATH
520 #define CONFIG_BOOTP_GATEWAY
521 #define CONFIG_BOOTP_HOSTNAME
525 * Command line configuration.
527 #include <config_cmd_default.h>
529 #define CONFIG_CMD_PING
530 #define CONFIG_CMD_I2C
531 #define CONFIG_CMD_MII
532 #define CONFIG_CMD_ELF
533 #define CONFIG_CMD_IRQ
534 #define CONFIG_CMD_SETEXPR
535 #define CONFIG_CMD_REGINFO
537 #if defined(CONFIG_PCI)
538 #define CONFIG_CMD_PCI
542 #undef CONFIG_WATCHDOG /* watchdog disabled */
547 #define CONFIG_FSL_ESDHC
548 #define CONFIG_FSL_ESDHC_PIN_MUX
549 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
550 #define CONFIG_CMD_MMC
551 #define CONFIG_GENERIC_MMC
552 #define CONFIG_CMD_EXT2
553 #define CONFIG_CMD_FAT
554 #define CONFIG_DOS_PARTITION
558 * Miscellaneous configurable options
560 #define CONFIG_SYS_LONGHELP /* undef to save memory */
561 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
562 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
563 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
564 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
565 #if defined(CONFIG_CMD_KGDB)
566 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
568 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
570 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
571 /* Print Buffer Size */
572 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
573 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
574 /* Boot Argument Buffer Size */
575 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
578 * For booting Linux, the board info and command line data
579 * have to be in the first 64 MB of memory, since this is
580 * the maximum mapped by the Linux kernel during initialization.
582 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
583 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
585 #if defined(CONFIG_CMD_KGDB)
586 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
587 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
591 * Environment Configuration
593 #define CONFIG_HOSTNAME mpc8569mds
594 #define CONFIG_ROOTPATH "/nfsroot"
595 #define CONFIG_BOOTFILE "your.uImage"
597 #define CONFIG_SERVERIP 192.168.1.1
598 #define CONFIG_GATEWAYIP 192.168.1.1
599 #define CONFIG_NETMASK 255.255.255.0
601 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
603 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
604 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
606 #define CONFIG_BAUDRATE 115200
608 #define CONFIG_EXTRA_ENV_SETTINGS \
610 "consoledev=ttyS0\0" \
611 "ramdiskaddr=600000\0" \
612 "ramdiskfile=your.ramdisk.u-boot\0" \
614 "fdtfile=your.fdt.dtb\0" \
615 "nfsargs=setenv bootargs root=/dev/nfs rw " \
616 "nfsroot=$serverip:$rootpath " \
617 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
618 "console=$consoledev,$baudrate $othbootargs\0" \
619 "ramargs=setenv bootargs root=/dev/ram rw " \
620 "console=$consoledev,$baudrate $othbootargs\0" \
622 #define CONFIG_NFSBOOTCOMMAND \
624 "tftp $loadaddr $bootfile;" \
625 "tftp $fdtaddr $fdtfile;" \
626 "bootm $loadaddr - $fdtaddr"
628 #define CONFIG_RAMBOOTCOMMAND \
630 "tftp $ramdiskaddr $ramdiskfile;" \
631 "tftp $loadaddr $bootfile;" \
632 "bootm $loadaddr $ramdiskaddr"
634 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
636 #endif /* __CONFIG_H */