2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8572ds board configuration file
14 #include "../board/freescale/common/ics307_clk.h"
16 #ifndef CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_TEXT_BASE 0xeff40000
20 #ifndef CONFIG_RESET_VECTOR_ADDRESS
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
24 #ifndef CONFIG_SYS_MONITOR_BASE
25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
28 /* High Level Configuration Options */
29 #define CONFIG_BOOKE 1 /* BOOKE */
30 #define CONFIG_E500 1 /* BOOKE e500 family */
31 #define CONFIG_MP 1 /* support multiple processors */
33 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
34 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
35 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
39 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
42 #define CONFIG_TSEC_ENET /* tsec ethernet support */
43 #define CONFIG_ENV_OVERWRITE
45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
47 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
50 * These can be toggled for performance analysis, otherwise use default.
52 #define CONFIG_L2_CACHE /* toggle L2 cache */
53 #define CONFIG_BTB /* toggle branch predition */
55 #define CONFIG_ENABLE_36BIT_PHYS 1
57 #ifdef CONFIG_PHYS_64BIT
58 #define CONFIG_ADDR_MAP 1
59 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
62 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
64 #define CONFIG_PANIC_HANG /* do not reset board on panic */
67 * Config the L2 Cache as L2 SRAM
69 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
70 #ifdef CONFIG_PHYS_64BIT
71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
73 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
75 #define CONFIG_SYS_L2_SIZE (512 << 10)
76 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
78 #define CONFIG_SYS_CCSRBAR 0xffe00000
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 #if defined(CONFIG_NAND_SPL)
82 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
86 #define CONFIG_VERY_BIG_RAM
87 #define CONFIG_SYS_FSL_DDR2
88 #undef CONFIG_FSL_DDR_INTERACTIVE
89 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
90 #define CONFIG_DDR_SPD
92 #define CONFIG_DDR_ECC
93 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
94 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_NUM_DDR_CONTROLLERS 2
100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
103 /* I2C addresses of SPD EEPROMs */
104 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
105 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
106 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
108 /* These are used when DDR doesn't use SPD. */
109 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
110 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
111 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
112 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
113 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
114 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
115 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
116 #define CONFIG_SYS_DDR_MODE_1 0x00440462
117 #define CONFIG_SYS_DDR_MODE_2 0x00000000
118 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
119 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
120 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
121 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
122 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
123 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
124 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
126 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
127 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
128 #define CONFIG_SYS_DDR_SBE 0x00010000
131 * Make sure required options are set
133 #ifndef CONFIG_SPD_EEPROM
134 #error ("CONFIG_SPD_EEPROM is required")
137 #undef CONFIG_CLOCKS_IN_MHZ
142 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
143 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
144 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
145 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
147 * Localbus cacheable (TBD)
148 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
150 * Localbus non-cacheable
151 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
152 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
153 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
154 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
155 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
156 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
160 * Local Bus Definitions
162 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
163 #ifdef CONFIG_PHYS_64BIT
164 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
166 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169 #define CONFIG_FLASH_BR_PRELIM \
170 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
171 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
173 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
174 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
177 #define CONFIG_SYS_FLASH_QUIET_TEST
178 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
182 #undef CONFIG_SYS_FLASH_CHECKSUM
183 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
184 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
186 #undef CONFIG_SYS_RAMBOOT
188 #define CONFIG_FLASH_CFI_DRIVER
189 #define CONFIG_SYS_FLASH_CFI
190 #define CONFIG_SYS_FLASH_EMPTY_INFO
191 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
193 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
195 #define CONFIG_HWCONFIG /* enable hwconfig */
196 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
197 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
198 #ifdef CONFIG_PHYS_64BIT
199 #define PIXIS_BASE_PHYS 0xfffdf0000ull
201 #define PIXIS_BASE_PHYS PIXIS_BASE
204 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
205 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
207 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
208 #define PIXIS_VER 0x1 /* Board version at offset 1 */
209 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
210 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
211 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
212 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
213 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
214 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
215 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
216 #define PIXIS_VCTL 0x10 /* VELA Control Register */
217 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
218 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
219 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
220 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
221 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
222 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
223 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
224 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
225 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
226 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
227 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
228 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
229 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
230 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
231 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
232 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
233 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
234 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
235 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
236 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
237 #define PIXIS_LED 0x25 /* LED Register */
239 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
241 /* old pixis referenced names */
242 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
243 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
244 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
245 #define PIXIS_VSPEED2_TSEC1SER 0x8
246 #define PIXIS_VSPEED2_TSEC2SER 0x4
247 #define PIXIS_VSPEED2_TSEC3SER 0x2
248 #define PIXIS_VSPEED2_TSEC4SER 0x1
249 #define PIXIS_VCFGEN1_TSEC1SER 0x20
250 #define PIXIS_VCFGEN1_TSEC2SER 0x20
251 #define PIXIS_VCFGEN1_TSEC3SER 0x20
252 #define PIXIS_VCFGEN1_TSEC4SER 0x20
253 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
254 | PIXIS_VSPEED2_TSEC2SER \
255 | PIXIS_VSPEED2_TSEC3SER \
256 | PIXIS_VSPEED2_TSEC4SER)
257 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
258 | PIXIS_VCFGEN1_TSEC2SER \
259 | PIXIS_VCFGEN1_TSEC3SER \
260 | PIXIS_VCFGEN1_TSEC4SER)
262 #define CONFIG_SYS_INIT_RAM_LOCK 1
263 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
264 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
266 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
267 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
269 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
270 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
272 #ifndef CONFIG_NAND_SPL
273 #define CONFIG_SYS_NAND_BASE 0xffa00000
274 #ifdef CONFIG_PHYS_64BIT
275 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
277 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
280 #define CONFIG_SYS_NAND_BASE 0xfff00000
281 #ifdef CONFIG_PHYS_64BIT
282 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
284 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
288 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
289 CONFIG_SYS_NAND_BASE + 0x40000, \
290 CONFIG_SYS_NAND_BASE + 0x80000,\
291 CONFIG_SYS_NAND_BASE + 0xC0000}
292 #define CONFIG_SYS_MAX_NAND_DEVICE 4
293 #define CONFIG_CMD_NAND 1
294 #define CONFIG_NAND_FSL_ELBC 1
295 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
296 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
297 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
299 /* NAND boot: 4K NAND loader config */
300 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
301 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
302 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
303 #define CONFIG_SYS_NAND_U_BOOT_START \
304 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
305 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
306 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
307 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
309 /* NAND flash config */
310 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
311 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
312 | BR_PS_8 /* Port Size = 8 bit */ \
313 | BR_MS_FCM /* MSEL = FCM */ \
315 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
316 | OR_FCM_PGS /* Large Page*/ \
324 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
325 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
326 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
327 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
328 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
329 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
330 | BR_PS_8 /* Port Size = 8 bit */ \
331 | BR_MS_FCM /* MSEL = FCM */ \
333 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
334 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
335 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
336 | BR_PS_8 /* Port Size = 8 bit */ \
337 | BR_MS_FCM /* MSEL = FCM */ \
339 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
341 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
343 | BR_PS_8 /* Port Size = 8 bit */ \
344 | BR_MS_FCM /* MSEL = FCM */ \
346 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
348 /* Serial Port - controlled on board with jumper J8
352 #define CONFIG_CONS_INDEX 1
353 #define CONFIG_SYS_NS16550_SERIAL
354 #define CONFIG_SYS_NS16550_REG_SIZE 1
355 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
356 #ifdef CONFIG_NAND_SPL
357 #define CONFIG_NS16550_MIN_FUNCTIONS
360 #define CONFIG_SYS_BAUDRATE_TABLE \
361 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
363 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
364 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
367 #define CONFIG_SYS_I2C
368 #define CONFIG_SYS_I2C_FSL
369 #define CONFIG_SYS_FSL_I2C_SPEED 400000
370 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
371 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
372 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
373 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
374 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
375 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
376 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
381 #define CONFIG_ID_EEPROM
382 #ifdef CONFIG_ID_EEPROM
383 #define CONFIG_SYS_I2C_EEPROM_NXID
385 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
386 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
387 #define CONFIG_SYS_EEPROM_BUS_NUM 1
391 * Memory space is mapped 1-1, but I/O space must start from 0.
394 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
395 #define CONFIG_SYS_PCIE3_NAME "ULI"
396 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
397 #ifdef CONFIG_PHYS_64BIT
398 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
399 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
401 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
402 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
404 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
405 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
406 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
407 #ifdef CONFIG_PHYS_64BIT
408 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
410 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
412 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
414 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
415 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
416 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
421 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
424 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
426 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
432 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
434 /* controller 1, Slot 1, tgtid 1, Base address a000 */
435 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
436 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
441 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
442 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
444 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
445 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
446 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
452 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
454 #if defined(CONFIG_PCI)
456 /*PCIE video card used*/
457 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
461 #if defined(CONFIG_VIDEO)
462 #define CONFIG_BIOSEMU
463 #define CONFIG_ATI_RADEON_FB
464 #define CONFIG_VIDEO_LOGO
465 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
468 #undef CONFIG_EEPRO100
471 #ifndef CONFIG_PCI_PNP
472 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
473 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
474 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
477 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
478 #define CONFIG_DOS_PARTITION
479 #define CONFIG_SCSI_AHCI
481 #ifdef CONFIG_SCSI_AHCI
482 #define CONFIG_LIBATA
483 #define CONFIG_SATA_ULI5288
484 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
485 #define CONFIG_SYS_SCSI_MAX_LUN 1
486 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
487 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
490 #endif /* CONFIG_PCI */
492 #if defined(CONFIG_TSEC_ENET)
494 #define CONFIG_MII 1 /* MII PHY management */
495 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
496 #define CONFIG_TSEC1 1
497 #define CONFIG_TSEC1_NAME "eTSEC1"
498 #define CONFIG_TSEC2 1
499 #define CONFIG_TSEC2_NAME "eTSEC2"
500 #define CONFIG_TSEC3 1
501 #define CONFIG_TSEC3_NAME "eTSEC3"
502 #define CONFIG_TSEC4 1
503 #define CONFIG_TSEC4_NAME "eTSEC4"
505 #define CONFIG_PIXIS_SGMII_CMD
506 #define CONFIG_FSL_SGMII_RISER 1
507 #define SGMII_RISER_PHY_OFFSET 0x1c
509 #ifdef CONFIG_FSL_SGMII_RISER
510 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
513 #define TSEC1_PHY_ADDR 0
514 #define TSEC2_PHY_ADDR 1
515 #define TSEC3_PHY_ADDR 2
516 #define TSEC4_PHY_ADDR 3
518 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
519 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
520 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
521 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
523 #define TSEC1_PHYIDX 0
524 #define TSEC2_PHYIDX 0
525 #define TSEC3_PHYIDX 0
526 #define TSEC4_PHYIDX 0
528 #define CONFIG_ETHPRIME "eTSEC1"
530 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
531 #endif /* CONFIG_TSEC_ENET */
537 #if defined(CONFIG_SYS_RAMBOOT)
540 #define CONFIG_ENV_IS_IN_FLASH 1
541 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
542 #define CONFIG_ENV_ADDR 0xfff80000
544 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
546 #define CONFIG_ENV_SIZE 0x2000
547 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
550 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
551 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
554 * Command line configuration.
556 #define CONFIG_CMD_ERRATA
557 #define CONFIG_CMD_IRQ
558 #define CONFIG_CMD_REGINFO
560 #if defined(CONFIG_PCI)
561 #define CONFIG_CMD_PCI
568 #define CONFIG_USB_EHCI
570 #ifdef CONFIG_USB_EHCI
571 #define CONFIG_USB_EHCI_PCI
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
573 #define CONFIG_PCI_EHCI_DEVICE 0
574 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
577 #undef CONFIG_WATCHDOG /* watchdog disabled */
580 * Miscellaneous configurable options
582 #define CONFIG_SYS_LONGHELP /* undef to save memory */
583 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
584 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
585 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
586 #if defined(CONFIG_CMD_KGDB)
587 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
589 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
591 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
592 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
593 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
596 * For booting Linux, the board info and command line data
597 * have to be in the first 64 MB of memory, since this is
598 * the maximum mapped by the Linux kernel during initialization.
600 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
601 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
603 #if defined(CONFIG_CMD_KGDB)
604 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
608 * Environment Configuration
610 #if defined(CONFIG_TSEC_ENET)
611 #define CONFIG_HAS_ETH0
612 #define CONFIG_HAS_ETH1
613 #define CONFIG_HAS_ETH2
614 #define CONFIG_HAS_ETH3
617 #define CONFIG_IPADDR 192.168.1.254
619 #define CONFIG_HOSTNAME unknown
620 #define CONFIG_ROOTPATH "/opt/nfsroot"
621 #define CONFIG_BOOTFILE "uImage"
622 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
624 #define CONFIG_SERVERIP 192.168.1.1
625 #define CONFIG_GATEWAYIP 192.168.1.1
626 #define CONFIG_NETMASK 255.255.255.0
628 /* default location for tftp and bootm */
629 #define CONFIG_LOADADDR 1000000
631 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
633 #define CONFIG_BAUDRATE 115200
635 #define CONFIG_EXTRA_ENV_SETTINGS \
636 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
638 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
639 "tftpflash=tftpboot $loadaddr $uboot; " \
640 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
642 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
644 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
646 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
648 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
650 "consoledev=ttyS0\0" \
651 "ramdiskaddr=2000000\0" \
652 "ramdiskfile=8572ds/ramdisk.uboot\0" \
653 "fdtaddr=1e00000\0" \
654 "fdtfile=8572ds/mpc8572ds.dtb\0" \
657 #define CONFIG_HDBOOT \
658 "setenv bootargs root=/dev/$bdev rw " \
659 "console=$consoledev,$baudrate $othbootargs;" \
660 "tftp $loadaddr $bootfile;" \
661 "tftp $fdtaddr $fdtfile;" \
662 "bootm $loadaddr - $fdtaddr"
664 #define CONFIG_NFSBOOTCOMMAND \
665 "setenv bootargs root=/dev/nfs rw " \
666 "nfsroot=$serverip:$rootpath " \
667 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
668 "console=$consoledev,$baudrate $othbootargs;" \
669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr - $fdtaddr"
673 #define CONFIG_RAMBOOTCOMMAND \
674 "setenv bootargs root=/dev/ram rw " \
675 "console=$consoledev,$baudrate $othbootargs;" \
676 "tftp $ramdiskaddr $ramdiskfile;" \
677 "tftp $loadaddr $bootfile;" \
678 "tftp $fdtaddr $fdtfile;" \
679 "bootm $loadaddr $ramdiskaddr $fdtaddr"
681 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
683 #endif /* __CONFIG_H */