2 * Copyright 2006, 2010-2011 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * SPDX-License-Identifier: GPL-2.0+
10 * MPC8641HPCN board configuration file
12 * Make sure you change the MAC address and other network params first,
13 * search for CONFIG_SERVERIP, etc. in this file.
19 /* High Level Configuration Options */
20 #define CONFIG_MP 1 /* support multiple processors */
21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22 #define CONFIG_ADDR_MAP 1 /* Use addr map */
25 * default CCSRBAR is at 0xff700000
26 * assume U-Boot is less than 0.5MB
28 #define CONFIG_SYS_TEXT_BASE 0xeff00000
31 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
35 * virtual address to be used for temporary mappings. There
36 * should be 128k free at this VA.
38 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
40 #define CONFIG_SYS_SRIO
41 #define CONFIG_SRIO1 /* SRIO port 1 */
43 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
44 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
48 #define CONFIG_TSEC_ENET /* tsec ethernet support */
49 #define CONFIG_ENV_OVERWRITE
51 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
52 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
53 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
55 #define CONFIG_ALTIVEC 1
58 * L2CR setup -- make sure this is right for your board!
62 #define L2_ENABLE (L2CR_L2E)
64 #ifndef CONFIG_SYS_CLK_FREQ
66 extern unsigned long get_board_sys_clk(unsigned long dummy);
68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
72 #define CONFIG_SYS_MEMTEST_END 0x00400000
75 * With the exception of PCI Memory and Rapid IO, most devices will simply
76 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
77 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
79 #ifdef CONFIG_PHYS_64BIT
80 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
82 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
86 * Base addresses -- Note these are effective addresses where the
87 * actual resources get mapped (not physical addresses)
89 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
92 /* Physical addresses */
93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
94 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
95 #define CONFIG_SYS_CCSRBAR_PHYS \
96 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
97 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
99 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
104 #define CONFIG_SYS_FSL_DDR2
105 #undef CONFIG_FSL_DDR_INTERACTIVE
106 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
107 #define CONFIG_DDR_SPD
109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
110 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
112 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
113 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
114 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
115 #define CONFIG_VERY_BIG_RAM
117 #define CONFIG_NUM_DDR_CONTROLLERS 2
118 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
119 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
122 * I2C addresses of SPD EEPROMs
124 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
125 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
126 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
127 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
130 * These are used when DDR doesn't use SPD.
132 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
136 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
137 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
138 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
139 #define CONFIG_SYS_DDR_MODE_1 0x00480432
140 #define CONFIG_SYS_DDR_MODE_2 0x00000000
141 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
142 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
143 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
144 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
145 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
146 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
147 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
149 #define CONFIG_ID_EEPROM
150 #define CONFIG_SYS_I2C_EEPROM_NXID
151 #define CONFIG_ID_EEPROM
152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
155 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
156 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
157 #define CONFIG_SYS_FLASH_BASE_PHYS \
158 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
159 CONFIG_SYS_PHYS_ADDR_HIGH)
161 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
163 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
164 | 0x00001001) /* port size 16bit */
165 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
167 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
168 | 0x00001001) /* port size 16bit */
169 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
171 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
172 | 0x00000801) /* port size 8bit */
173 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
176 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
177 * The PIXIS and CF by themselves aren't large enough to take up the 128k
178 * required for the smallest BAT mapping, so there's a 64k hole.
180 #define CONFIG_SYS_LBC_BASE 0xffde0000
181 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
183 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
184 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
185 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
186 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
187 CONFIG_SYS_PHYS_ADDR_HIGH)
188 #define PIXIS_SIZE 0x00008000 /* 32k */
189 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
190 #define PIXIS_VER 0x1 /* Board version at offset 1 */
191 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
192 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
193 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
194 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
195 #define PIXIS_VCTL 0x10 /* VELA Control Register */
196 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
197 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
198 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
199 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
200 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
201 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
202 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
203 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
204 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
205 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
207 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
208 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
209 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
212 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
214 #undef CONFIG_SYS_FLASH_CHECKSUM
215 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
216 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
218 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
220 #define CONFIG_FLASH_CFI_DRIVER
221 #define CONFIG_SYS_FLASH_CFI
222 #define CONFIG_SYS_FLASH_EMPTY_INFO
224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
225 #define CONFIG_SYS_RAMBOOT
227 #undef CONFIG_SYS_RAMBOOT
230 #if defined(CONFIG_SYS_RAMBOOT)
231 #undef CONFIG_SPD_EEPROM
232 #define CONFIG_SYS_SDRAM_SIZE 256
235 #undef CONFIG_CLOCKS_IN_MHZ
237 #define CONFIG_SYS_INIT_RAM_LOCK 1
238 #ifndef CONFIG_SYS_INIT_RAM_LOCK
239 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
241 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
243 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
245 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
246 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
248 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
249 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
252 #define CONFIG_CONS_INDEX 1
253 #define CONFIG_SYS_NS16550_SERIAL
254 #define CONFIG_SYS_NS16550_REG_SIZE 1
255 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
257 #define CONFIG_SYS_BAUDRATE_TABLE \
258 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
266 #define CONFIG_SYS_I2C
267 #define CONFIG_SYS_I2C_FSL
268 #define CONFIG_SYS_FSL_I2C_SPEED 400000
269 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
270 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
271 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
276 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
277 #ifdef CONFIG_PHYS_64BIT
278 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
279 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
281 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
282 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
284 #define CONFIG_SYS_SRIO1_MEM_PHYS \
285 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
286 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
287 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
291 * Addresses are mapped 1-1.
294 #define CONFIG_SYS_PCIE1_NAME "ULI"
295 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
296 #ifdef CONFIG_PHYS_64BIT
297 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
298 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
299 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
301 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
302 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
303 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
305 #define CONFIG_SYS_PCIE1_MEM_PHYS \
306 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
307 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
308 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
309 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
310 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
311 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
312 #define CONFIG_SYS_PCIE1_IO_PHYS \
313 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
314 CONFIG_SYS_PHYS_ADDR_HIGH)
315 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
317 #ifdef CONFIG_PHYS_64BIT
319 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
320 * This will increase the amount of PCI address space available for
323 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
325 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
326 + CONFIG_SYS_PCIE1_MEM_SIZE)
328 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
329 + CONFIG_SYS_PCIE1_MEM_SIZE)
330 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
331 + CONFIG_SYS_PCIE1_MEM_SIZE)
332 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
333 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
334 + CONFIG_SYS_PCIE1_MEM_SIZE)
335 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
336 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
337 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
338 + CONFIG_SYS_PCIE1_IO_SIZE)
339 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
340 + CONFIG_SYS_PCIE1_IO_SIZE)
341 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
342 + CONFIG_SYS_PCIE1_IO_SIZE)
343 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
345 #if defined(CONFIG_PCI)
347 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
349 #undef CONFIG_EEPRO100
352 /************************************************************
354 ************************************************************/
355 #define CONFIG_PCI_OHCI 1
356 #define CONFIG_USB_OHCI_NEW 1
357 #define CONFIG_SYS_USB_EVENT_POLL 1
358 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
359 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
360 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
362 /*PCIE video card used*/
363 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
365 /*PCI video card used*/
366 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
370 #if defined(CONFIG_VIDEO)
371 #define CONFIG_BIOSEMU
372 #define CONFIG_ATI_RADEON_FB
373 #define CONFIG_VIDEO_LOGO
374 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
377 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
379 #define CONFIG_DOS_PARTITION
380 #define CONFIG_SCSI_AHCI
382 #ifdef CONFIG_SCSI_AHCI
383 #define CONFIG_LIBATA
384 #define CONFIG_SATA_ULI5288
385 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
386 #define CONFIG_SYS_SCSI_MAX_LUN 1
387 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
388 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
391 #endif /* CONFIG_PCI */
393 #if defined(CONFIG_TSEC_ENET)
395 #define CONFIG_MII 1 /* MII PHY management */
397 #define CONFIG_TSEC1 1
398 #define CONFIG_TSEC1_NAME "eTSEC1"
399 #define CONFIG_TSEC2 1
400 #define CONFIG_TSEC2_NAME "eTSEC2"
401 #define CONFIG_TSEC3 1
402 #define CONFIG_TSEC3_NAME "eTSEC3"
403 #define CONFIG_TSEC4 1
404 #define CONFIG_TSEC4_NAME "eTSEC4"
406 #define TSEC1_PHY_ADDR 0
407 #define TSEC2_PHY_ADDR 1
408 #define TSEC3_PHY_ADDR 2
409 #define TSEC4_PHY_ADDR 3
410 #define TSEC1_PHYIDX 0
411 #define TSEC2_PHYIDX 0
412 #define TSEC3_PHYIDX 0
413 #define TSEC4_PHYIDX 0
414 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
416 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
417 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
419 #define CONFIG_ETHPRIME "eTSEC1"
421 #endif /* CONFIG_TSEC_ENET */
423 #ifdef CONFIG_PHYS_64BIT
424 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
425 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
427 /* Put physical address into the BAT format */
428 #define BAT_PHYS_ADDR(low, high) \
429 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
430 /* Convert high/low pairs to actual 64-bit value */
431 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
433 /* 32-bit systems just ignore the "high" bits */
434 #define BAT_PHYS_ADDR(low, high) (low)
435 #define PAIRED_PHYS_TO_PHYS(low, high) (low)
441 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
442 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
445 * BAT1 LBC (PIXIS/CF)
447 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
448 CONFIG_SYS_PHYS_ADDR_HIGH) \
449 | BATL_PP_RW | BATL_CACHEINHIBIT | \
451 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
453 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
454 CONFIG_SYS_PHYS_ADDR_HIGH) \
455 | BATL_PP_RW | BATL_MEMCOHERENCE)
456 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
459 * BAT2 PCIE1 and PCIE1 MEM
461 * BAT2 Rapidio Memory
464 #define CONFIG_PCI_INDIRECT_BRIDGE
465 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
466 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
467 | BATL_PP_RW | BATL_CACHEINHIBIT \
468 | BATL_GUARDEDSTORAGE)
469 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
471 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
472 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
473 | BATL_PP_RW | BATL_CACHEINHIBIT)
474 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
475 #else /* CONFIG_RIO */
476 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
477 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
478 | BATL_PP_RW | BATL_CACHEINHIBIT | \
480 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
482 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
483 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
484 | BATL_PP_RW | BATL_CACHEINHIBIT)
485 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
491 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
492 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
493 | BATL_PP_RW | BATL_CACHEINHIBIT \
494 | BATL_GUARDEDSTORAGE)
495 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
497 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
498 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
499 | BATL_PP_RW | BATL_CACHEINHIBIT)
500 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
502 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
503 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
504 | BATL_PP_RW | BATL_CACHEINHIBIT \
505 | BATL_GUARDEDSTORAGE)
506 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
507 | BATU_BL_1M | BATU_VS | BATU_VP)
508 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
509 | BATL_PP_RW | BATL_CACHEINHIBIT)
510 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
514 * BAT4 PCIE1_IO and PCIE2_IO
516 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
517 CONFIG_SYS_PHYS_ADDR_HIGH) \
518 | BATL_PP_RW | BATL_CACHEINHIBIT \
519 | BATL_GUARDEDSTORAGE)
520 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
522 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
523 CONFIG_SYS_PHYS_ADDR_HIGH) \
524 | BATL_PP_RW | BATL_CACHEINHIBIT)
525 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
528 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
530 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
531 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
532 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
533 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
538 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
539 CONFIG_SYS_PHYS_ADDR_HIGH) \
540 | BATL_PP_RW | BATL_CACHEINHIBIT \
541 | BATL_GUARDEDSTORAGE)
542 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
544 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
545 CONFIG_SYS_PHYS_ADDR_HIGH) \
546 | BATL_PP_RW | BATL_MEMCOHERENCE)
547 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
549 /* Map the last 1M of flash where we're running from reset */
550 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
551 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
552 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
553 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
555 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
558 * BAT7 FREE - used later for tmp mappings
560 #define CONFIG_SYS_DBAT7L 0x00000000
561 #define CONFIG_SYS_DBAT7U 0x00000000
562 #define CONFIG_SYS_IBAT7L 0x00000000
563 #define CONFIG_SYS_IBAT7U 0x00000000
568 #ifndef CONFIG_SYS_RAMBOOT
569 #define CONFIG_ENV_IS_IN_FLASH 1
570 #define CONFIG_ENV_ADDR \
571 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
572 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
574 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
575 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
577 #define CONFIG_ENV_SIZE 0x2000
579 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
580 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
585 #define CONFIG_BOOTP_BOOTFILESIZE
586 #define CONFIG_BOOTP_BOOTPATH
587 #define CONFIG_BOOTP_GATEWAY
588 #define CONFIG_BOOTP_HOSTNAME
591 * Command line configuration.
593 #define CONFIG_CMD_REGINFO
595 #if defined(CONFIG_PCI)
596 #define CONFIG_CMD_PCI
600 #undef CONFIG_WATCHDOG /* watchdog disabled */
603 * Miscellaneous configurable options
605 #define CONFIG_SYS_LONGHELP /* undef to save memory */
606 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
607 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
609 #if defined(CONFIG_CMD_KGDB)
610 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
612 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
615 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
616 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
617 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
620 * For booting Linux, the board info and command line data
621 * have to be in the first 8 MB of memory, since this is
622 * the maximum mapped by the Linux kernel during initialization.
624 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
625 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
627 #if defined(CONFIG_CMD_KGDB)
628 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
632 * Environment Configuration
635 #define CONFIG_HAS_ETH0 1
636 #define CONFIG_HAS_ETH1 1
637 #define CONFIG_HAS_ETH2 1
638 #define CONFIG_HAS_ETH3 1
640 #define CONFIG_IPADDR 192.168.1.100
642 #define CONFIG_HOSTNAME unknown
643 #define CONFIG_ROOTPATH "/opt/nfsroot"
644 #define CONFIG_BOOTFILE "uImage"
645 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
647 #define CONFIG_SERVERIP 192.168.1.1
648 #define CONFIG_GATEWAYIP 192.168.1.1
649 #define CONFIG_NETMASK 255.255.255.0
651 /* default location for tftp and bootm */
652 #define CONFIG_LOADADDR 0x10000000
654 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
656 #define CONFIG_BAUDRATE 115200
658 #define CONFIG_EXTRA_ENV_SETTINGS \
660 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
661 "tftpflash=tftpboot $loadaddr $uboot; " \
662 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
664 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
666 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
668 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
670 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
672 "consoledev=ttyS0\0" \
673 "ramdiskaddr=0x18000000\0" \
674 "ramdiskfile=your.ramdisk.u-boot\0" \
675 "fdtaddr=0x17c00000\0" \
676 "fdtfile=mpc8641_hpcn.dtb\0" \
677 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
678 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
681 #define CONFIG_NFSBOOTCOMMAND \
682 "setenv bootargs root=/dev/nfs rw " \
683 "nfsroot=$serverip:$rootpath " \
684 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
685 "console=$consoledev,$baudrate $othbootargs;" \
686 "tftp $loadaddr $bootfile;" \
687 "tftp $fdtaddr $fdtfile;" \
688 "bootm $loadaddr - $fdtaddr"
690 #define CONFIG_RAMBOOTCOMMAND \
691 "setenv bootargs root=/dev/ram rw " \
692 "console=$consoledev,$baudrate $othbootargs;" \
693 "tftp $ramdiskaddr $ramdiskfile;" \
694 "tftp $loadaddr $bootfile;" \
695 "tftp $fdtaddr $fdtfile;" \
696 "bootm $loadaddr $ramdiskaddr $fdtaddr"
698 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
700 #endif /* __CONFIG_H */