2 * A collection of structures, addresses, and values associated with
3 * the Motorola MPC8xxADS board. Copied from the FADS config.
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
9 * 1999-nov-26: The FADS is using the following physical memorymap:
11 * ff020000 -> ff02ffff : pcmcia
12 * ff010000 -> ff01ffff : BCSR connected to CS1
13 * ff000000 -> ff00ffff : IMAP internal in the cpu
14 * fe000000 -> fennnnnn : flash connected to CS0
15 * 00000000 -> nnnnnnnn : sdram connected to CS4
18 /* ------------------------------------------------------------------------- */
21 * board/config.h - configuration options, board specific
28 * High Level Configuration Options
33 #define CONFIG_MPC86xADS 1 /* new ADS */
34 #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
36 /* new 86xADS only - pick one of these */
37 #define CONFIG_MPC866T 1
40 #undef CONFIG_MPC859DSL
43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44 #undef CONFIG_8xx_CONS_SMC2
45 #undef CONFIG_8xx_CONS_NONE
46 #define CONFIG_BAUDRATE 38400
47 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49 #ifdef CONFIG_MPC86xADS
50 # define CFG_8XX_FACT 5 /* Multiply by 5 */
51 # define CFG_8XX_XIN 10000000 /* 10 MHz in */
52 #else /* ! CONFIG_MPC86xADS */
54 # define CFG_8XX_FACT 12 /* Multiply by 12 */
55 # define CFG_8XX_XIN 4000000 /* 4 MHz in */
57 # define CFG_8XX_FACT 10 /* Multiply by 10 */
58 # define CFG_8XX_XIN 5000000 /* 5 MHz in */
60 #endif /* ! CONFIG_MPC86xADS */
62 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
64 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
65 /* in general, we always know this for FADS+new ADS anyway */
66 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
69 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
71 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
74 #undef CONFIG_BOOTARGS
75 #define CONFIG_BOOTCOMMAND \
77 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
78 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
81 #undef CONFIG_WATCHDOG /* watchdog disabled */
83 /* ATA / IDE and partition support */
84 #define CONFIG_MAC_PARTITION 1
85 #define CONFIG_DOS_PARTITION 1
86 #define CONFIG_ISO_PARTITION 1
88 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
89 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
90 #undef CONFIG_IDE_LED /* LED for ide not supported */
91 #undef CONFIG_IDE_RESET /* reset for ide not supported */
94 * New MPC86xADS provides two Ethernet connectivity options:
95 * 10Mbit/s on SCC1 and 100Mbit/s on FEC. All new PQ1 chips
96 * has got FEC so FEC is the default.
98 #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
99 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
100 #ifdef CONFIG_FEC_ENET
101 #define CFG_DISCOVER_PHY
103 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
104 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
107 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
114 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
115 #include <cmd_confdefs.h>
118 * Miscellaneous configurable options
120 #undef CFG_LONGHELP /* undef to save memory */
121 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
122 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
123 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
125 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
127 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
128 #define CFG_MAXARGS 16 /* max number of command args */
129 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
131 #define CFG_LOAD_ADDR 0x00100000
133 #define CFG_HZ 1000 /* decr freq: 1 ms ticks */
135 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
142 /*-----------------------------------------------------------------------
143 * Internal Memory Mapped Register
145 #define CFG_IMMR 0xFF000000
146 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
148 /*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
151 #define CFG_INIT_RAM_ADDR CFG_IMMR
152 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
153 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
154 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
155 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
157 /*-----------------------------------------------------------------------
158 * Start addresses for the final memory configuration
159 * (Set up by the startup code)
160 * Please note that CFG_SDRAM_BASE _must_ start at 0
162 #define CFG_SDRAM_BASE 0x00000000
163 #if defined(CONFIG_MPC86xADS) /* new ADS */
164 #define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */
165 #elif defined(CONFIG_FADS) /* old/new FADS */
166 #define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */
168 #define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
171 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
173 #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
175 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
176 #endif /* CFG_SDRAM_SIZE */
179 * For booting Linux, the board info and command line data
180 * have to be in the first 8 MB of memory, since this is
181 * the maximum mapped by the Linux kernel during initialization.
183 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
184 /*-----------------------------------------------------------------------
187 #define CFG_FLASH_BASE TEXT_BASE
188 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
190 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
191 #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
193 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
196 #define CFG_ENV_IS_IN_FLASH 1
197 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
198 #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
199 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
201 #define CFG_MONITOR_BASE CFG_FLASH_BASE
202 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
203 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
205 /*-----------------------------------------------------------------------
206 * Cache Configuration
208 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
209 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
210 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
213 /*-----------------------------------------------------------------------
214 * SYPCR - System Protection Control 11-9
215 * SYPCR can only be written once after reset!
216 *-----------------------------------------------------------------------
217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
219 #if defined(CONFIG_WATCHDOG)
220 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
223 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
226 /*-----------------------------------------------------------------------
227 * SIUMCR - SIU Module Configuration 11-6
228 *-----------------------------------------------------------------------
229 * PCMCIA config., multi-function pin tri-state
231 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
233 /*-----------------------------------------------------------------------
234 * TBSCR - Time Base Status and Control 11-26
235 *-----------------------------------------------------------------------
236 * Clear Reference Interrupt Status, Timebase freezing enabled
238 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
240 /*-----------------------------------------------------------------------
241 * PISCR - Periodic Interrupt Status and Control 11-31
242 *-----------------------------------------------------------------------
243 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
245 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
247 /*-----------------------------------------------------------------------
248 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
249 *-----------------------------------------------------------------------
250 * set the PLL, the low-power modes and the reset control (15-29)
252 #define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \
253 PLPRCR_SPLSS | PLPRCR_TEXPS)
255 /*-----------------------------------------------------------------------
256 * SCCR - System Clock and reset Control Register 15-27
257 *-----------------------------------------------------------------------
258 * Set clock output, timebase and RTC source and divider,
259 * power management and some other internal clocks
261 #define SCCR_MASK SCCR_EBDF11
262 #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
264 /*-----------------------------------------------------------------------
266 *-----------------------------------------------------------------------
271 /* Because of the way the 860 starts up and assigns CS0 the
272 * entire address space, we have to set the memory controller
273 * differently. Normally, you write the option register
274 * first, and then enable the chip select by writing the
275 * base register. For CS0, you must write the base register
276 * first, followed by the option register.
280 * Init Memory Controller:
285 /* the other CS:s are determined by looking at parameters in BCSRx */
287 #define BCSR_ADDR ((uint) 0xFF010000)
288 #define BCSR_SIZE ((uint)(64 * 1024))
290 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
292 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
293 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
295 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
296 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
298 /* BCSRx - Board Control and Status Registers */
299 #define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
300 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
303 * Internal Definitions
307 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
308 #define BOOTFLAG_WARM 0x02 /* Software reboot */
310 /* values according to the manual */
312 #define PCMCIA_MEM_ADDR ((uint)0xff020000)
313 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
315 #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
316 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
317 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
318 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
319 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
321 /* FADS bitvalues by Helmut Buchsbaum
322 * see MPC8xxADS User's Manual for a proper description
323 * of the following structures
326 #define BCSR0_ERB ((uint)0x80000000)
327 #define BCSR0_IP ((uint)0x40000000)
328 #define BCSR0_BDIS ((uint)0x10000000)
329 #define BCSR0_BPS_MASK ((uint)0x0C000000)
330 #define BCSR0_ISB_MASK ((uint)0x01800000)
331 #define BCSR0_DBGC_MASK ((uint)0x00600000)
332 #define BCSR0_DBPC_MASK ((uint)0x00180000)
333 #define BCSR0_EBDF_MASK ((uint)0x00060000)
335 #define BCSR1_FLASH_EN ((uint)0x80000000)
336 #define BCSR1_DRAM_EN ((uint)0x40000000)
337 #define BCSR1_ETHEN ((uint)0x20000000)
338 #define BCSR1_IRDEN ((uint)0x10000000)
339 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
340 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
341 #define BCSR1_BCSR_EN ((uint)0x02000000)
342 #define BCSR1_RS232EN_1 ((uint)0x01000000)
343 #define BCSR1_PCCEN ((uint)0x00800000)
344 #define BCSR1_PCCVCC0 ((uint)0x00400000)
345 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
346 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
347 #define BCSR1_RS232EN_2 ((uint)0x00040000)
348 #define BCSR1_SDRAM_EN ((uint)0x00020000)
349 #define BCSR1_PCCVCC1 ((uint)0x00010000)
351 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
352 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
353 #define BCSR2_DRAM_PD_SHIFT (23)
354 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
355 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
357 #define BCSR3_DBID_MASK ((ushort)0x3800)
358 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
359 #define BCSR3_BREVNR0 ((ushort)0x0080)
360 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
361 #define BCSR3_BREVN1 ((ushort)0x0008)
362 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
364 #define BCSR4_ETHLOOP ((uint)0x80000000)
365 #define BCSR4_TFPLDL ((uint)0x40000000)
366 #define BCSR4_TPSQEL ((uint)0x20000000)
367 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
368 #define BCSR4_FETH_EN ((uint)0x08000000)
369 #define BCSR4_FETHCFG0 ((uint)0x04000000)
370 #define BCSR4_FETHFDE ((uint)0x02000000)
371 #define BCSR4_FETHCFG1 ((uint)0x00400000)
372 #define BCSR4_FETHRST ((uint)0x00200000)
374 #define CONFIG_DRAM_50MHZ 1
375 #define CONFIG_SDRAM_50MHZ 1
377 /* We don't use the 8259.
379 #define NR_8259_INTS 0
383 #define _MACH_8xx (_MACH_fads)
385 #define CONFIG_DISK_SPINUP_TIME 1000000
388 /* PCMCIA configuration */
391 #define PCMCIA_SLOT_A 1
394 #define CFG_PCMCIA_MEM_ADDR (0x50000000)
395 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
396 #define CFG_PCMCIA_DMA_ADDR (0x54000000)
397 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
398 #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
399 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
400 #define CFG_PCMCIA_IO_ADDR (0x5C000000)
401 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
402 /* we have 8 windows, we take everything up to 60000000 */
404 #define CFG_ATA_IDE0_OFFSET 0x0000
406 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
408 /* Offset for data I/O */
409 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
410 /* Offset for normal register accesses */
411 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
412 /* Offset for alternate registers */
413 #define CFG_ATA_ALT_OFFSET 0x0000
414 /*#define CFG_ATA_ALT_OFFSET 0x0100 */
417 #endif /* __CONFIG_H */