2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #define CONFIG_MPC5xxx 1
33 #define CONFIG_MPC5200 1
35 #ifndef CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_TEXT_BASE 0xFF800000
39 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
41 #define BOOTFLAG_COLD 0x01
42 #define BOOTFLAG_WARM 0x02
44 #define CONFIG_MISC_INIT_R 1
46 #define CONFIG_SYS_CACHELINE_SIZE 32
47 #ifdef CONFIG_CMD_KGDB
48 #define CONFIG_SYS_CACHELINE_SHIFT 5
51 #define CONFIG_PSC_CONSOLE 1
52 #define CONFIG_BAUDRATE 115200
53 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
56 #define CONFIG_PCI_PNP 1
57 #undef CONFIG_PCI_SCAN_SHOW
58 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
60 #define CONFIG_PCI_MEM_BUS 0x40000000
61 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
62 #define CONFIG_PCI_MEM_SIZE 0x10000000
64 #define CONFIG_PCI_IO_BUS 0x50000000
65 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
66 #define CONFIG_PCI_IO_SIZE 0x01000000
68 #define CONFIG_SYS_XLB_PIPELINING 1
69 #define CONFIG_HIGH_BATS 1
71 #define MV_CI mvBlueCOUGAR-P
72 #define MV_VCI mvBlueCOUGAR-P
73 #define MV_FPGA_DATA 0xff860000
74 #define MV_FPGA_SIZE 0
75 #define MV_KERNEL_ADDR 0xffd00000
76 #define MV_INITRD_ADDR 0xff900000
77 #define MV_INITRD_LENGTH 0x00400000
78 #define MV_SCRATCH_ADDR 0x00000000
79 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
80 #define MV_SCRIPT_ADDR 0xff840000
81 #define MV_SCRIPT_ADDR2 0xff850000
82 #define MV_DTB_ADDR 0xfffc0000
84 #define CONFIG_SHOW_BOOT_PROGRESS 1
86 #define MV_KERNEL_ADDR_RAM 0x00100000
87 #define MV_DTB_ADDR_RAM 0x00600000
88 #define MV_INITRD_ADDR_RAM 0x01000000
90 /* pass open firmware flat tree */
91 #define CONFIG_OF_LIBFDT 1
92 #define CONFIG_OF_BOARD_SETUP 1
94 #define OF_CPU "PowerPC,5200@0"
95 #define OF_SOC "soc5200@f0000000"
96 #define OF_TBCLK (bd->bi_busfreq / 4)
97 #define MV_DTB_NAME mvbc-p.dtb
98 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
103 #include <config_cmd_default.h>
105 #define CONFIG_CMD_CACHE
106 #define CONFIG_CMD_NET
107 #define CONFIG_CMD_PING
108 #define CONFIG_CMD_DHCP
109 #define CONFIG_CMD_SDRAM
110 #define CONFIG_CMD_PCI
111 #define CONFIG_CMD_FPGA
112 #define CONFIG_CMD_I2C
114 #undef CONFIG_WATCHDOG
116 #define CONFIG_BOOTP_VENDOREX
117 #define CONFIG_BOOTP_SUBNETMASK
118 #define CONFIG_BOOTP_GATEWAY
119 #define CONFIG_BOOTP_DNS
120 #define CONFIG_BOOTP_DNS2
121 #define CONFIG_BOOTP_HOSTNAME
122 #define CONFIG_BOOTP_BOOTFILESIZE
123 #define CONFIG_BOOTP_BOOTPATH
124 #define CONFIG_BOOTP_NTPSERVER
125 #define CONFIG_BOOTP_RANDOM_DELAY
126 #define CONFIG_BOOTP_SEND_HOSTNAME
131 #define CONFIG_BOOTDELAY 2
132 #define CONFIG_AUTOBOOT_KEYED
133 #define CONFIG_AUTOBOOT_STOP_STR "s"
134 #define CONFIG_ZERO_BOOTDELAY_CHECK
135 #define CONFIG_RESET_TO_RETRY 1000
137 #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
138 then source ${script_addr}; \
139 else source ${script_addr2}; \
142 #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
143 #define CONFIG_ENV_OVERWRITE
145 #define XMK_STR(x) #x
146 #define MK_STR(x) XMK_STR(x)
148 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
156 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
157 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
158 "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
159 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
160 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
161 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
162 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
163 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
164 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
165 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
166 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
167 "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
168 "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
169 "mv_version=" U_BOOT_VERSION "\0" \
170 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
171 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
173 "use_static_ipaddr=no\0" \
174 "static_ipaddr=192.168.90.10\0" \
175 "static_netmask=255.255.255.0\0" \
176 "static_gateway=0.0.0.0\0" \
177 "initrd_name=uInitrd.mvbc-p-rfs\0" \
181 "tried_bootfromflash=no\0" \
182 "tried_bootfromnet=no\0" \
185 "mvbcdma_debug=0\0" \
187 "propdev_debug=0\0" \
197 * IPB Bus clocking configuration.
199 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
200 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
203 * Flash configuration
205 #undef CONFIG_FLASH_16BIT
206 #define CONFIG_SYS_FLASH_CFI
207 #define CONFIG_FLASH_CFI_DRIVER
208 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
209 #define CONFIG_SYS_FLASH_EMPTY_INFO
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 50000
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1
215 #define CONFIG_SYS_MAX_FLASH_SECT 256
217 #define CONFIG_SYS_LOWBOOT
218 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
219 #define CONFIG_SYS_FLASH_SIZE 0x00800000
222 * Environment settings
224 #define CONFIG_ENV_IS_IN_FLASH
225 #undef CONFIG_SYS_FLASH_PROTECTION
227 #define CONFIG_ENV_ADDR 0xFFFE0000
228 #define CONFIG_ENV_SIZE 0x10000
229 #define CONFIG_ENV_SECT_SIZE 0x10000
230 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
231 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
236 #define CONFIG_SYS_MBAR 0xF0000000
237 #define CONFIG_SYS_SDRAM_BASE 0x00000000
238 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
240 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
241 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
243 #define CONFIG_SYS_GBL_DATA_SIZE 128
244 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
245 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
247 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
248 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
249 #define CONFIG_SYS_RAMBOOT 1
252 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
253 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
254 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
255 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
260 #define CONFIG_HARD_I2C 1
261 #define CONFIG_SYS_I2C_MODULE 1
262 #define CONFIG_SYS_I2C_SPEED 86000
263 #define CONFIG_SYS_I2C_SLAVE 0x7F
266 * Ethernet configuration
268 #define CONFIG_NET_MULTI
269 #define CONFIG_NET_RETRY_COUNT 5
272 #define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
273 #undef CONFIG_MPC5xxx_FEC
274 #undef CONFIG_PHY_ADDR
275 #define CONFIG_NETDEV eth0
278 * Miscellaneous configurable options
280 #define CONFIG_SYS_HUSH_PARSER
281 #define CONFIG_CMDLINE_EDITING
282 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
283 #undef CONFIG_SYS_LONGHELP
284 #define CONFIG_SYS_PROMPT "=> "
285 #ifdef CONFIG_CMD_KGDB
286 #define CONFIG_SYS_CBSIZE 1024
288 #define CONFIG_SYS_CBSIZE 256
290 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
291 #define CONFIG_SYS_MAXARGS 16
292 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
294 #define CONFIG_SYS_MEMTEST_START 0x00800000
295 #define CONFIG_SYS_MEMTEST_END 0x02f00000
297 #define CONFIG_SYS_HZ 1000
299 /* default load address */
300 #define CONFIG_SYS_LOAD_ADDR 0x02000000
301 /* default location for tftp and bootm */
302 #define CONFIG_LOADADDR 0x00200000
305 * Various low-level settings
307 #define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
309 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
310 #define CONFIG_SYS_HID0_FINAL HID0_ICE
312 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
313 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
314 #define CONFIG_SYS_BOOTCS_CFG 0x00047800
315 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
316 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
318 #define CONFIG_SYS_CS_BURST 0x000000f0
319 #define CONFIG_SYS_CS_DEADCYCLE 0x33333303
321 #define CONFIG_SYS_RESET_ADDRESS 0x00000100
324 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
325 #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
326 #define CONFIG_FPGA_ALTERA 1
327 #define CONFIG_FPGA_CYCLON2 1
328 #define CONFIG_FPGA_COUNT 1