2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10 * U-Boot port on NetTA4 board
16 #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
17 #error Unsupported CONFIG_NETPHONE version
21 * High Level Configuration Options
25 #define CONFIG_MPC870 1 /* This is a MPC885 CPU */
26 #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
28 #define CONFIG_SYS_TEXT_BASE 0x40000000
30 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
31 #undef CONFIG_8xx_CONS_SMC2
32 #undef CONFIG_8xx_CONS_NONE
34 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
36 /* #define CONFIG_XIN 10000000 */
37 #define CONFIG_XIN 50000000
38 /* #define MPC8XX_HZ 120000000 */
39 #define MPC8XX_HZ 66666666
41 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
44 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
51 #define CONFIG_PREBOOT "echo;"
53 #undef CONFIG_BOOTARGS
54 #define CONFIG_BOOTCOMMAND \
56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
61 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
62 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64 #undef CONFIG_WATCHDOG /* watchdog disabled */
66 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
68 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
69 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
74 #define CONFIG_BOOTP_SUBNETMASK
75 #define CONFIG_BOOTP_GATEWAY
76 #define CONFIG_BOOTP_HOSTNAME
77 #define CONFIG_BOOTP_BOOTPATH
78 #define CONFIG_BOOTP_BOOTFILESIZE
79 #define CONFIG_BOOTP_NISDOMAIN
81 #undef CONFIG_MAC_PARTITION
82 #undef CONFIG_DOS_PARTITION
84 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
86 #define FEC_ENET 1 /* eth.c needs it that way... */
87 #undef CONFIG_SYS_DISCOVER_PHY
89 #define CONFIG_MII_INIT 1
90 #define CONFIG_RMII 1 /* use RMII interface */
92 #define CONFIG_ETHER_ON_FEC1 1
93 #define CONFIG_FEC1_PHY 8 /* phy address of FEC */
94 #define CONFIG_FEC1_PHY_NORXERR 1
96 #define CONFIG_ETHER_ON_FEC2 1
97 #define CONFIG_FEC2_PHY 4
98 #define CONFIG_FEC2_PHY_NORXERR 1
100 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
104 * Command line configuration.
106 #include <config_cmd_default.h>
108 #define CONFIG_CMD_DHCP
109 #define CONFIG_CMD_PING
110 #define CONFIG_CMD_MII
111 #define CONFIG_CMD_CDP
114 #define CONFIG_BOARD_EARLY_INIT_F 1
115 #define CONFIG_MISC_INIT_R
118 * Miscellaneous configurable options
120 #define CONFIG_SYS_LONGHELP /* undef to save memory */
122 #define CONFIG_SYS_HUSH_PARSER 1
124 #if defined(CONFIG_CMD_KGDB)
125 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
127 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
133 #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
134 #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
136 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
139 * Low Level Configuration Settings
140 * (address mappings, register initial values, etc.)
141 * You should know what you are doing if you make changes here.
143 /*-----------------------------------------------------------------------
144 * Internal Memory Mapped Register
146 #define CONFIG_SYS_IMMR 0xFF000000
148 /*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
151 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
152 #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
156 /*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
161 #define CONFIG_SYS_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_FLASH_BASE 0x40000000
164 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
166 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
170 #if CONFIG_NETPHONE_VERSION == 2
171 #define CONFIG_SYS_FLASH_BASE4 0x40080000
174 #define CONFIG_SYS_RESET_ADDRESS 0x80000000
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
181 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
183 /*-----------------------------------------------------------------------
186 #if CONFIG_NETPHONE_VERSION == 1
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
188 #elif CONFIG_NETPHONE_VERSION == 2
189 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
193 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
196 #define CONFIG_ENV_IS_IN_FLASH 1
197 #define CONFIG_ENV_SECT_SIZE 0x10000
199 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
200 #define CONFIG_ENV_SIZE 0x4000
202 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
203 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
205 /*-----------------------------------------------------------------------
206 * Cache Configuration
208 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
209 #if defined(CONFIG_CMD_KGDB)
210 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
213 /*-----------------------------------------------------------------------
214 * SYPCR - System Protection Control 11-9
215 * SYPCR can only be written once after reset!
216 *-----------------------------------------------------------------------
217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
219 #if defined(CONFIG_WATCHDOG)
220 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
223 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
226 /*-----------------------------------------------------------------------
227 * SIUMCR - SIU Module Configuration 11-6
228 *-----------------------------------------------------------------------
229 * PCMCIA config., multi-function pin tri-state
231 #ifndef CONFIG_CAN_DRIVER
232 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
233 #else /* we must activate GPL5 in the SIUMCR for CAN */
234 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
235 #endif /* CONFIG_CAN_DRIVER */
237 /*-----------------------------------------------------------------------
238 * TBSCR - Time Base Status and Control 11-26
239 *-----------------------------------------------------------------------
240 * Clear Reference Interrupt Status, Timebase freezing enabled
242 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
244 /*-----------------------------------------------------------------------
245 * RTCSC - Real-Time Clock Status and Control Register 11-27
246 *-----------------------------------------------------------------------
248 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
250 /*-----------------------------------------------------------------------
251 * PISCR - Periodic Interrupt Status and Control 11-31
252 *-----------------------------------------------------------------------
253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
255 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
257 /*-----------------------------------------------------------------------
258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
259 *-----------------------------------------------------------------------
260 * Reset PLL lock status sticky bit, timer expired status bit and timer
261 * interrupt status bit
265 #if CONFIG_XIN == 10000000
267 #if MPC8XX_HZ == 120000000
268 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
269 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
271 #elif MPC8XX_HZ == 100000000
272 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
273 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
275 #elif MPC8XX_HZ == 50000000
276 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
277 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
279 #elif MPC8XX_HZ == 25000000
280 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
281 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
283 #elif MPC8XX_HZ == 40000000
284 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
285 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
287 #elif MPC8XX_HZ == 75000000
288 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
289 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
292 #error unsupported CPU freq for XIN = 10MHz
295 #elif CONFIG_XIN == 50000000
297 #if MPC8XX_HZ == 120000000
298 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
299 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
301 #elif MPC8XX_HZ == 100000000
302 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
303 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
305 #elif MPC8XX_HZ == 66666666
306 #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
307 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
310 #error unsupported CPU freq for XIN = 50MHz
315 #error unsupported XIN freq
320 *-----------------------------------------------------------------------
321 * SCCR - System Clock and reset Control Register 15-27
322 *-----------------------------------------------------------------------
323 * Set clock output, timebase and RTC source and divider,
324 * power management and some other internal clocks
326 * Note: When TBS == 0 the timebase is independent of current cpu clock.
329 #define SCCR_MASK SCCR_EBDF11
330 #if MPC8XX_HZ > 66666666
331 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
332 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
333 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
334 SCCR_DFALCD00 | SCCR_EBDF01)
336 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
337 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
338 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
342 /*-----------------------------------------------------------------------
344 *-----------------------------------------------------------------------
347 /*#define CONFIG_SYS_DER 0x2002000F*/
348 #define CONFIG_SYS_DER 0
351 * Init Memory Controller:
353 * BR0/1 and OR0/1 (FLASH)
356 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
358 /* used to re-map FLASH both when starting from SRAM or FLASH:
359 * restrict access enough to keep SRAM working (if any)
360 * but not too much to meddle with FLASH accesses
362 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
363 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
365 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
366 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
368 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
369 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
370 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
372 #if CONFIG_NETPHONE_VERSION == 2
374 #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
376 #define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
377 #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
378 #define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
383 * BR3 and OR3 (SDRAM)
386 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
387 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
389 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
390 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
392 #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
393 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
396 * Memory Periodic Timer Prescaler
400 * Memory Periodic Timer Prescaler
402 * The Divider for PTA (refresh timer) configuration is based on an
403 * example SDRAM configuration (64 MBit, one bank). The adjustment to
404 * the number of chip selects (NCS) and the actually needed refresh
405 * rate is done by setting MPTPR.
407 * PTA is calculated from
408 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
410 * gclk CPU clock (not bus clock!)
411 * Trefresh Refresh cycle * 4 (four word bursts used)
413 * 4096 Rows from SDRAM example configuration
414 * 1000 factor s -> ms
415 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
416 * 4 Number of refresh cycles per period
417 * 64 Refresh cycle in ms per number of rows
418 * --------------------------------------------
419 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
421 * 50 MHz => 50.000.000 / Divider = 98
422 * 66 Mhz => 66.000.000 / Divider = 129
423 * 80 Mhz => 80.000.000 / Divider = 156
426 #define CONFIG_SYS_MAMR_PTA 234
429 * For 16 MBit, refresh rates could be 31.3 us
430 * (= 64 ms / 2K = 125 / quad bursts).
431 * For a simpler initialization, 15.6 us is used instead.
433 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
434 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
436 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
437 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
439 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
440 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
441 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
444 * MAMR settings for SDRAM
448 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
449 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
450 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
453 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
454 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
457 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
459 /****************************************************************/
461 #define DSP_SIZE 0x00010000 /* 64K */
462 #define NAND_SIZE 0x00010000 /* 64K */
464 #define DSP_BASE 0xF1000000
465 #define NAND_BASE 0xF1010000
467 /*****************************************************************************/
469 #define CONFIG_SYS_DIRECT_FLASH_TFTP
471 /*****************************************************************************/
473 #if CONFIG_NETPHONE_VERSION == 1
474 #define STATUS_LED_BIT 0x00000008 /* bit 28 */
475 #elif CONFIG_NETPHONE_VERSION == 2
476 #define STATUS_LED_BIT 0x00000080 /* bit 24 */
479 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
480 #define STATUS_LED_STATE STATUS_LED_BLINKING
482 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
483 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
489 /* led_id_t is unsigned int mask */
490 typedef unsigned int led_id_t;
492 #define __led_toggle(_msk) \
494 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
497 #define __led_set(_msk, _st) \
500 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
502 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
505 #define __led_init(msk, st) __led_set(msk, st)
509 /***********************************************************************************************************
511 ----------------------------------------------------------------------------------------------
513 (V1) version 1 of the board
514 (V2) version 2 of the board
516 ----------------------------------------------------------------------------------------------
520 +------+----------------+--------+------------------------------------------------------------
521 | # | Name | Type | Comment
522 +------+----------------+--------+------------------------------------------------------------
523 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
524 | PA7 | DSP_INT | Output | DSP interrupt
525 | PA10 | DSP_RESET | Output | DSP reset
526 | PA14 | USBOE | Output | USB (1)
527 | PA15 | USBRXD | Output | USB (1)
528 | PB19 | BT_RTS | Output | Bluetooth (0)
529 | PB23 | BT_CTS | Output | Bluetooth (0)
530 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
531 | PB27 | SPICS_DISP | Output | Display chip select
532 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
533 | PB29 | SPI_TXD | Output | SPI Data Tx
534 | PB30 | SPI_CLK | Output | SPI Clock
535 | PC10 | DISPA0 | Output | Display A0
536 | PC11 | BACKLIGHT | Output | Display backlit
537 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
538 | | IO_RESET | Output | (V2) General I/O reset
539 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
540 | | HOOK | Input | (V2) Hook input interrupt
541 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
542 | | F_RY_BY | Input | (V2) NAND F_RY_BY
543 | PE17 | F_ALE | Output | NAND F_ALE
544 | PE18 | F_CLE | Output | NAND F_CLE
545 | PE20 | F_CE | Output | NAND F_CE
546 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
547 | | LED | Output | (V2) LED
548 | PE27 | SPICS_ER | Output | External serial register CS
549 | PE28 | LEDIO1 | Output | (V1) LED
550 | | BKBR1 | Input | (V2) Keyboard input scan
551 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
552 | | BKBR2 | Input | (V2) Keyboard input scan
553 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
554 | | BKBR3 | Input | (V2) Keyboard input scan
555 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
556 | | BKBR4 | Input | (V2) Keyboard input scan
557 +------+----------------+--------+---------------------------------------------------
559 ----------------------------------------------------------------------------------------------
561 Serial register input:
563 +------+----------------+------------------------------------------------------------
565 +------+----------------+------------------------------------------------------------
566 | 0 | BKBR1 | (V1) Keyboard input scan
567 | 1 | BKBR3 | (V1) Keyboard input scan
568 | 2 | BKBR4 | (V1) Keyboard input scan
569 | 3 | BKBR2 | (V1) Keyboard input scan
570 | 4 | HOOK | (V1) Hook switch
571 | 5 | BT_LINK | (V1) Bluetooth link status
572 | 6 | HOST_WAKE | (V1) Bluetooth host wake up
573 | 7 | OK_ETH | (V1) Cisco inline power OK status
574 +------+----------------+------------------------------------------------------------
576 ----------------------------------------------------------------------------------------------
578 Serial register output:
580 +------+----------------+------------------------------------------------------------
582 +------+----------------+------------------------------------------------------------
583 | 0 | KEY1 | Keyboard output scan
584 | 1 | KEY2 | Keyboard output scan
585 | 2 | KEY3 | Keyboard output scan
586 | 3 | KEY4 | Keyboard output scan
587 | 4 | KEY5 | Keyboard output scan
588 | 5 | KEY6 | Keyboard output scan
589 | 6 | KEY7 | Keyboard output scan
590 | 7 | BT_WAKE | Bluetooth wake up
591 +------+----------------+------------------------------------------------------------
593 ----------------------------------------------------------------------------------------------
597 +------+----------------+------------------------------------------------------------
599 +------+----------------+------------------------------------------------------------
600 | CS0 | CS0 | Boot flash
601 | CS1 | CS_FLASH | NAND flash
603 | CS3 | DCS_DRAM | DRAM
604 | CS4 | CS_FLASH2 | (V2) 2nd flash
605 +------+----------------+------------------------------------------------------------
607 ----------------------------------------------------------------------------------------------
611 +------+----------------+------------------------------------------------------------
613 +------+----------------+------------------------------------------------------------
614 | IRQ1 | IRQ_DSP | DSP interrupt
615 | IRQ3 | S_INTER | DUSLIC ???
616 | IRQ4 | F_RY_BY | NAND
617 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
618 +------+----------------+------------------------------------------------------------
620 ----------------------------------------------------------------------------------------------
622 Interrupts on PCMCIA pins:
624 +------+----------------+------------------------------------------------------------
626 +------+----------------+------------------------------------------------------------
627 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
628 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
629 | IP_A2| RMII1_MDINT | PHY interrupt for #1
630 | IP_A3| RMII2_MDINT | PHY interrupt for #2
631 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
632 | IP_A6| OK_ETH | (V2) Cisco inline power OK
633 +------+----------------+------------------------------------------------------------
635 *************************************************************************************************/
637 #define CONFIG_SED156X 1 /* use SED156X */
638 #define CONFIG_SED156X_PG12864Q 1 /* type of display used */
640 /* serial interfacing macros */
642 #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
643 #define SED156X_SPI_RXD_MASK 0x00000008
645 #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
646 #define SED156X_SPI_TXD_MASK 0x00000004
648 #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
649 #define SED156X_SPI_CLK_MASK 0x00000002
651 #define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
652 #define SED156X_CS_MASK 0x00000010
654 #define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
655 #define SED156X_A0_MASK 0x0020
657 /*************************************************************************************************/
659 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
660 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
661 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
663 /*************************************************************************************************/
665 /* use board specific hardware */
666 #undef CONFIG_WATCHDOG /* watchdog disabled */
667 #define CONFIG_HW_WATCHDOG
668 #define CONFIG_SHOW_ACTIVITY
670 /*************************************************************************************************/
672 /* phone console configuration */
674 #define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */
676 /*************************************************************************************************/
678 #define CONFIG_CDP_DEVICE_ID 20
679 #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
680 #define CONFIG_CDP_PORT_ID "eth%d"
681 #define CONFIG_CDP_CAPABILITIES 0x00000010
682 #define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
683 #define CONFIG_CDP_PLATFORM "Intracom NetPhone"
684 #define CONFIG_CDP_TRIGGER 0x20020001
685 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
686 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
688 /*************************************************************************************************/
690 #define CONFIG_AUTO_COMPLETE 1
692 /*************************************************************************************************/
694 #define CONFIG_CRC32_VERIFY 1
696 /*************************************************************************************************/
698 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
700 /*************************************************************************************************/
701 #endif /* __CONFIG_H */