2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
33 * High Level Configuration Options
37 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
38 #define CONFIG_NETTA 1 /* ...on a NetTA board */
40 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41 #undef CONFIG_8xx_CONS_SMC2
42 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
46 /* #define CONFIG_XIN 10000000 */
47 #define CONFIG_XIN 50000000
48 #define MPC8XX_HZ 120000000
49 /* #define MPC8XX_HZ 100000000 */
50 /* #define MPC8XX_HZ 50000000 */
51 /* #define MPC8XX_HZ 80000000 */
53 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
63 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
65 #undef CONFIG_BOOTARGS
66 #define CONFIG_BOOTCOMMAND \
68 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
72 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
73 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #define CONFIG_HW_WATCHDOG
78 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
80 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
82 #undef CONFIG_MAC_PARTITION
83 #undef CONFIG_DOS_PARTITION
85 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
87 #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
88 #define FEC_ENET 1 /* eth.c needs it that way... */
89 #undef CFG_DISCOVER_PHY /* do not discover phys */
91 #define CONFIG_RMII 1 /* use RMII interface */
93 #if defined(CONFIG_NETTA_ISDN)
94 #define CONFIG_ETHER_ON_FEC1 1
95 #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
96 #define CONFIG_FEC1_PHY_NORXERR 1
97 #undef CONFIG_ETHER_ON_FEC2
99 #define CONFIG_ETHER_ON_FEC1 1
100 #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
101 #define CONFIG_FEC1_PHY_NORXERR 1
102 #define CONFIG_ETHER_ON_FEC2 1
103 #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
104 #define CONFIG_FEC2_PHY_NORXERR 1
107 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
110 #define CONFIG_POST (CFG_POST_MEMORY | \
116 * Command line configuration.
118 #include <config_cmd_default.h>
120 #define CONFIG_CMD_CDP
121 #define CONFIG_CMD_DHCP
122 #define CONFIG_CMD_DIAG
123 #define CONFIG_CMD_FAT
124 #define CONFIG_CMD_IDE
125 #define CONFIG_CMD_JFFS2
126 #define CONFIG_CMD_MII
127 #define CONFIG_CMD_NAND
128 #define CONFIG_CMD_NFS
129 #define CONFIG_CMD_PCMCIA
130 #define CONFIG_CMD_PING
133 #define CONFIG_BOARD_EARLY_INIT_F 1
134 #define CONFIG_MISC_INIT_R
137 * Miscellaneous configurable options
139 #define CFG_LONGHELP /* undef to save memory */
140 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
142 #define CFG_HUSH_PARSER 1
143 #define CFG_PROMPT_HUSH_PS2 "> "
145 #if defined(CONFIG_CMD_KGDB)
146 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
151 #define CFG_MAXARGS 16 /* max number of command args */
152 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
154 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
155 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
157 #define CFG_LOAD_ADDR 0x100000 /* default load address */
159 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
161 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
164 * Low Level Configuration Settings
165 * (address mappings, register initial values, etc.)
166 * You should know what you are doing if you make changes here.
168 /*-----------------------------------------------------------------------
169 * Internal Memory Mapped Register
171 #define CFG_IMMR 0xFF000000
173 /*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM)
176 #define CFG_INIT_RAM_ADDR CFG_IMMR
177 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
178 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
179 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
180 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
182 /*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
185 * Please note that CFG_SDRAM_BASE _must_ start at 0
187 #define CFG_SDRAM_BASE 0x00000000
188 #define CFG_FLASH_BASE 0x40000000
190 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
192 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
194 #define CFG_MONITOR_BASE CFG_FLASH_BASE
195 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204 /*-----------------------------------------------------------------------
207 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
208 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
210 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
211 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
213 #define CFG_ENV_IS_IN_FLASH 1
214 #define CFG_ENV_SECT_SIZE 0x10000
216 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
217 #define CFG_ENV_OFFSET 0
218 #define CFG_ENV_SIZE 0x4000
220 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
221 #define CFG_ENV_OFFSET_REDUND 0
222 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
224 /*-----------------------------------------------------------------------
225 * Cache Configuration
227 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
228 #if defined(CONFIG_CMD_KGDB)
229 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
232 /*-----------------------------------------------------------------------
233 * SYPCR - System Protection Control 11-9
234 * SYPCR can only be written once after reset!
235 *-----------------------------------------------------------------------
236 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
238 #if defined(CONFIG_WATCHDOG)
239 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
240 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
242 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
245 /*-----------------------------------------------------------------------
246 * SIUMCR - SIU Module Configuration 11-6
247 *-----------------------------------------------------------------------
248 * PCMCIA config., multi-function pin tri-state
250 #ifndef CONFIG_CAN_DRIVER
251 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
252 #else /* we must activate GPL5 in the SIUMCR for CAN */
253 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
254 #endif /* CONFIG_CAN_DRIVER */
256 /*-----------------------------------------------------------------------
257 * TBSCR - Time Base Status and Control 11-26
258 *-----------------------------------------------------------------------
259 * Clear Reference Interrupt Status, Timebase freezing enabled
261 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
263 /*-----------------------------------------------------------------------
264 * RTCSC - Real-Time Clock Status and Control Register 11-27
265 *-----------------------------------------------------------------------
267 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
269 /*-----------------------------------------------------------------------
270 * PISCR - Periodic Interrupt Status and Control 11-31
271 *-----------------------------------------------------------------------
272 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
274 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
276 /*-----------------------------------------------------------------------
277 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
278 *-----------------------------------------------------------------------
279 * Reset PLL lock status sticky bit, timer expired status bit and timer
280 * interrupt status bit
284 #if CONFIG_XIN == 10000000
286 #if MPC8XX_HZ == 120000000
287 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
288 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
290 #elif MPC8XX_HZ == 100000000
291 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
292 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
294 #elif MPC8XX_HZ == 50000000
295 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
296 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
298 #elif MPC8XX_HZ == 25000000
299 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
300 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
302 #elif MPC8XX_HZ == 40000000
303 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
304 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
306 #elif MPC8XX_HZ == 75000000
307 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
308 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
311 #error unsupported CPU freq for XIN = 10MHz
314 #elif CONFIG_XIN == 50000000
316 #if MPC8XX_HZ == 120000000
317 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
318 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
320 #elif MPC8XX_HZ == 100000000
321 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
322 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
324 #elif MPC8XX_HZ == 80000000
325 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
326 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
328 #elif MPC8XX_HZ == 50000000
329 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
330 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
333 #error unsupported CPU freq for XIN = 50MHz
338 #error unsupported XIN freq
343 *-----------------------------------------------------------------------
344 * SCCR - System Clock and reset Control Register 15-27
345 *-----------------------------------------------------------------------
346 * Set clock output, timebase and RTC source and divider,
347 * power management and some other internal clocks
349 * Note: When TBS == 0 the timebase is independent of current cpu clock.
352 #define SCCR_MASK SCCR_EBDF11
353 #if MPC8XX_HZ > 66666666
354 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
355 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
356 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
357 SCCR_DFALCD00 | SCCR_EBDF01)
359 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
360 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
361 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
365 /*-----------------------------------------------------------------------
367 *-----------------------------------------------------------------------
370 /*#define CFG_DER 0x2002000F*/
374 * Init Memory Controller:
376 * BR0/1 and OR0/1 (FLASH)
379 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
381 /* used to re-map FLASH both when starting from SRAM or FLASH:
382 * restrict access enough to keep SRAM working (if any)
383 * but not too much to meddle with FLASH accesses
385 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
386 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
388 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
389 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
391 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
392 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
393 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
396 * BR3 and OR3 (SDRAM)
399 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
400 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
402 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
403 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
405 #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
406 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
409 * Memory Periodic Timer Prescaler
413 * Memory Periodic Timer Prescaler
415 * The Divider for PTA (refresh timer) configuration is based on an
416 * example SDRAM configuration (64 MBit, one bank). The adjustment to
417 * the number of chip selects (NCS) and the actually needed refresh
418 * rate is done by setting MPTPR.
420 * PTA is calculated from
421 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
423 * gclk CPU clock (not bus clock!)
424 * Trefresh Refresh cycle * 4 (four word bursts used)
426 * 4096 Rows from SDRAM example configuration
427 * 1000 factor s -> ms
428 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
429 * 4 Number of refresh cycles per period
430 * 64 Refresh cycle in ms per number of rows
431 * --------------------------------------------
432 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
434 * 50 MHz => 50.000.000 / Divider = 98
435 * 66 Mhz => 66.000.000 / Divider = 129
436 * 80 Mhz => 80.000.000 / Divider = 156
439 #if MPC8XX_HZ == 120000000
440 #define CFG_MAMR_PTA 234
441 #elif MPC8XX_HZ == 100000000
442 #define CFG_MAMR_PTA 195
443 #elif MPC8XX_HZ == 80000000
444 #define CFG_MAMR_PTA 156
445 #elif MPC8XX_HZ == 50000000
446 #define CFG_MAMR_PTA 98
448 #error Unknown frequency
453 * For 16 MBit, refresh rates could be 31.3 us
454 * (= 64 ms / 2K = 125 / quad bursts).
455 * For a simpler initialization, 15.6 us is used instead.
457 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
458 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
460 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
461 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
463 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
464 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
465 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
468 * MAMR settings for SDRAM
472 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
473 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
477 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
478 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
482 * Internal Definitions
486 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
487 #define BOOTFLAG_WARM 0x02 /* Software reboot */
489 #define CONFIG_ARTOS /* include ARTOS support */
491 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
493 /***********************************************************************************************************
497 +------+----------------+--------+------------------------------------------------------------
498 | # | Name | Type | Comment
499 +------+----------------+--------+------------------------------------------------------------
500 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
501 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
502 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
503 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
504 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
505 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
506 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
507 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
508 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
509 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
510 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
511 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
512 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
513 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
514 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
515 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
516 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
517 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
518 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
519 | PB21 | LEDIO | Output | Led mode indication for PHY
520 | PB22 | UART_CTS | Input | UART CTS
521 | PB23 | UART_RTS | Output | UART RTS
522 | PB24 | UART_RX | Periph | UART Data Rx
523 | PB25 | UART_TX | Periph | UART Data Tx
524 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
525 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
526 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
527 | PB29 | SPI_TXD | Output | SPI Data Tx
528 | PB30 | SPI_CLK | Output | SPI Clock
529 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
530 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
531 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
532 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
533 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
534 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
535 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
536 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
537 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
538 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
539 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
540 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
541 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
542 | PD3 | F_ALE | Output | NAND
543 | PD4 | F_CLE | Output | NAND
544 | PD5 | F_CE | Output | NAND
545 | PD6 | DSP_INT | Output | DSP debug interrupt
546 | PD7 | DSP_RESET | Output | DSP reset
547 | PD8 | RMII_MDC | Periph | MII mgt clock
548 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
549 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
550 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
551 | PD12 | FSC2 | Periph | IDL2 frame sync
552 | PD13 | DGRANT2 | Input | D channel grant from S #2
553 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
554 | PD15 | TP700 | Output | Testpoint for software debugging
555 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
556 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
557 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
558 | | DCL2 | Periph | NetRoute: PCM clock #2
559 | PE17 | TP703 | Output | Testpoint for software debugging
560 | PE18 | DGRANT1 | Input | D channel grant from S #1
561 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
562 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
563 | PE20 | FSC1 | Periph | IDL1 frame sync
564 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
565 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
566 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
567 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
568 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
569 | PE26 | RMII2-RXDV | Periph | FEC2 valid
570 | PE27 | DREQ2 | Output | D channel request for S #2.
571 | PE28 | FPGA_DONE | Input | FPGA done signal
572 | PE29 | FPGA_INIT | Output | FPGA init signal
573 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
575 +------+----------------+--------+---------------------------------------------------
579 +------+----------------+------------------------------------------------------------
581 +------+----------------+------------------------------------------------------------
582 | CS0 | CS0 | Boot flash
583 | CS1 | CS_FLASH | NAND flash
585 | CS3 | DCS_DRAM | DRAM
586 | CS4 | CS_ER1 | External output register
587 +------+----------------+------------------------------------------------------------
591 +------+----------------+------------------------------------------------------------
593 +------+----------------+------------------------------------------------------------
594 | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
595 | IRQ3 | IRQ_DSP | DSP interrupt
596 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
597 +------+----------------+------------------------------------------------------------
599 *************************************************************************************************/
601 #define DSP_SIZE 0x00010000 /* 64K */
602 #define NAND_SIZE 0x00010000 /* 64K */
603 #define ER_SIZE 0x00010000 /* 64K */
604 #define DUMMY_SIZE 0x00010000 /* 64K */
606 #define DSP_BASE 0xF1000000
607 #define NAND_BASE 0xF1010000
608 #define ER_BASE 0xF1020000
609 #define DUMMY_BASE 0xF1FF0000
611 /****************************************************************/
614 #define CFG_NAND_LEGACY
615 #define CFG_NAND_BASE NAND_BASE
616 #define CONFIG_MTD_NAND_VERIFY_WRITE
617 #define CONFIG_MTD_NAND_UNSAFE
619 #define CFG_MAX_NAND_DEVICE 1
620 /* #define NAND_NO_RB */
622 #define SECTORSIZE 512
623 #define ADDR_COLUMN 1
625 #define ADDR_COLUMN_PAGE 3
626 #define NAND_ChipID_UNKNOWN 0x00
627 #define NAND_MAX_FLOORS 1
628 #define NAND_MAX_CHIPS 1
630 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
631 #define NAND_DISABLE_CE(nand) \
633 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
636 #define NAND_ENABLE_CE(nand) \
638 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
641 #define NAND_CTL_CLRALE(nandptr) \
643 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
646 #define NAND_CTL_SETALE(nandptr) \
648 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
651 #define NAND_CTL_CLRCLE(nandptr) \
653 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
656 #define NAND_CTL_SETCLE(nandptr) \
658 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
662 #define NAND_WAIT_READY(nand) \
664 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
669 #define NAND_WAIT_READY(nand) udelay(12)
672 #define WRITE_NAND_COMMAND(d, adr) \
674 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
677 #define WRITE_NAND_ADDRESS(d, adr) \
679 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
682 #define WRITE_NAND(d, adr) \
684 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
687 #define READ_NAND(adr) \
688 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
690 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
691 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
697 /* No command line, one static partition, whole device */
698 #undef CONFIG_JFFS2_CMDLINE
699 #define CONFIG_JFFS2_DEV "nand0"
700 #define CONFIG_JFFS2_PART_SIZE 0x00100000
701 #define CONFIG_JFFS2_PART_OFFSET 0x00200000
703 /* mtdparts command line support */
704 /* Note: fake mtd_id used, no linux mtd map file */
706 #define CONFIG_JFFS2_CMDLINE
707 #define MTDIDS_DEFAULT "nand0=netta-nand"
708 #define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
711 /*****************************************************************************/
713 #define CFG_DIRECT_FLASH_TFTP
714 #define CFG_DIRECT_NAND_TFTP
716 /*****************************************************************************/
719 /*-----------------------------------------------------------------------
721 *-----------------------------------------------------------------------
724 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
725 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
726 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
727 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
728 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
729 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
730 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
731 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
733 /*-----------------------------------------------------------------------
734 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
735 *-----------------------------------------------------------------------
738 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
740 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
741 #undef CONFIG_IDE_LED /* LED for ide not supported */
742 #undef CONFIG_IDE_RESET /* reset for ide not supported */
744 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
745 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
747 #define CFG_ATA_IDE0_OFFSET 0x0000
749 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
751 /* Offset for data I/O */
752 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
754 /* Offset for normal register accesses */
755 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
757 /* Offset for alternate registers */
758 #define CFG_ATA_ALT_OFFSET 0x0100
760 #define CONFIG_MAC_PARTITION
761 #define CONFIG_DOS_PARTITION
764 /*************************************************************************************************/
766 #define CONFIG_CDP_DEVICE_ID 20
767 #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
768 #define CONFIG_CDP_PORT_ID "eth%d"
769 #define CONFIG_CDP_CAPABILITIES 0x00000010
770 #define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__
771 #define CONFIG_CDP_PLATFORM "Intracom NetTA"
772 #define CONFIG_CDP_TRIGGER 0x20020001
773 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
774 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
776 /*************************************************************************************************/
778 #define CONFIG_AUTO_COMPLETE 1
780 /*************************************************************************************************/
782 #define CONFIG_CRC32_VERIFY 1
784 /*************************************************************************************************/
786 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
788 /*************************************************************************************************/
790 #endif /* __CONFIG_H */