3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetVia board
33 * High Level Configuration Options
37 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
38 #define CONFIG_NETVIA 1 /* ...on a NetVia board */
40 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
45 #define CONFIG_8xx_CONS_NONE
46 #define CONFIG_MAX3100_SERIAL
49 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
51 #define CONFIG_XIN 10000000
52 #define CONFIG_8xx_GCLK_FREQ 80000000
55 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
62 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
64 #undef CONFIG_BOOTARGS
65 #define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
68 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
71 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
72 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
74 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
78 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
79 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
82 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
84 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
86 #undef CONFIG_MAC_PARTITION
87 #undef CONFIG_DOS_PARTITION
89 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
93 * Command line configuration.
95 #include <config_cmd_default.h>
97 #define CONFIG_CMD_DHCP
98 #define CONFIG_CMD_PING
100 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
101 #define CONFIG_CMD_NAND
105 #define CONFIG_BOARD_EARLY_INIT_F 1
106 #define CONFIG_MISC_INIT_R
109 * Miscellaneous configurable options
111 #define CFG_LONGHELP /* undef to save memory */
112 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
113 #if defined(CONFIG_CMD_KGDB)
114 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
116 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119 #define CFG_MAXARGS 16 /* max number of command args */
120 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
122 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
123 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
125 #define CFG_LOAD_ADDR 0x100000 /* default load address */
127 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
129 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132 * Low Level Configuration Settings
133 * (address mappings, register initial values, etc.)
134 * You should know what you are doing if you make changes here.
136 /*-----------------------------------------------------------------------
137 * Internal Memory Mapped Register
139 #define CFG_IMMR 0xFF000000
141 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM)
144 #define CFG_INIT_RAM_ADDR CFG_IMMR
145 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
146 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
147 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
148 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
150 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration
152 * (Set up by the startup code)
153 * Please note that CFG_SDRAM_BASE _must_ start at 0
155 #define CFG_SDRAM_BASE 0x00000000
156 #define CFG_FLASH_BASE 0x40000000
158 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
162 #define CFG_MONITOR_BASE CFG_FLASH_BASE
163 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
166 * For booting Linux, the board info and command line data
167 * have to be in the first 8 MB of memory, since this is
168 * the maximum mapped by the Linux kernel during initialization.
170 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
172 /*-----------------------------------------------------------------------
175 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
176 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
178 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
179 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
181 #define CFG_ENV_IS_IN_FLASH 1
182 #define CFG_ENV_SECT_SIZE 0x10000
184 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
185 #define CFG_ENV_OFFSET 0
186 #define CFG_ENV_SIZE 0x4000
188 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
189 #define CFG_ENV_OFFSET_REDUND 0
190 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
192 /*-----------------------------------------------------------------------
193 * Cache Configuration
195 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
196 #if defined(CONFIG_CMD_KGDB)
197 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
200 /*-----------------------------------------------------------------------
201 * SYPCR - System Protection Control 11-9
202 * SYPCR can only be written once after reset!
203 *-----------------------------------------------------------------------
204 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
206 #if defined(CONFIG_WATCHDOG)
207 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
208 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
210 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
213 /*-----------------------------------------------------------------------
214 * SIUMCR - SIU Module Configuration 11-6
215 *-----------------------------------------------------------------------
216 * PCMCIA config., multi-function pin tri-state
218 #ifndef CONFIG_CAN_DRIVER
219 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
220 #else /* we must activate GPL5 in the SIUMCR for CAN */
221 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
222 #endif /* CONFIG_CAN_DRIVER */
224 /*-----------------------------------------------------------------------
225 * TBSCR - Time Base Status and Control 11-26
226 *-----------------------------------------------------------------------
227 * Clear Reference Interrupt Status, Timebase freezing enabled
229 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
231 /*-----------------------------------------------------------------------
232 * RTCSC - Real-Time Clock Status and Control Register 11-27
233 *-----------------------------------------------------------------------
235 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
237 /*-----------------------------------------------------------------------
238 * PISCR - Periodic Interrupt Status and Control 11-31
239 *-----------------------------------------------------------------------
240 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
242 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
244 /*-----------------------------------------------------------------------
245 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
246 *-----------------------------------------------------------------------
247 * Reset PLL lock status sticky bit, timer expired status bit and timer
248 * interrupt status bit
251 *-----------------------------------------------------------------------
252 * SCCR - System Clock and reset Control Register 15-27
253 *-----------------------------------------------------------------------
254 * Set clock output, timebase and RTC source and divider,
255 * power management and some other internal clocks
258 #define SCCR_MASK SCCR_EBDF11
260 #if CONFIG_8xx_GCLK_FREQ == 50000000
262 #define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
263 #define CFG_SCCR (SCCR_TBS | \
264 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
265 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
268 #elif CONFIG_8xx_GCLK_FREQ == 80000000
270 #define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
271 #define CFG_SCCR (SCCR_TBS | \
272 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
273 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
274 SCCR_DFALCD00 | SCCR_EBDF01)
278 /*-----------------------------------------------------------------------
280 *-----------------------------------------------------------------------
283 /*#define CFG_DER 0x2002000F*/
287 * Init Memory Controller:
289 * BR0/1 and OR0/1 (FLASH)
292 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
294 /* used to re-map FLASH both when starting from SRAM or FLASH:
295 * restrict access enough to keep SRAM working (if any)
296 * but not too much to meddle with FLASH accesses
298 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
299 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
301 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
302 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
304 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
305 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
306 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
309 * BR3 and OR3 (SDRAM)
312 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
313 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
315 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
316 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
318 #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
319 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
322 * Memory Periodic Timer Prescaler
325 /* periodic timer for refresh */
326 #define CFG_MAMR_PTA 208
328 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
329 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
332 * MAMR settings for SDRAM
336 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
337 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
338 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
341 * Internal Definitions
345 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
346 #define BOOTFLAG_WARM 0x02 /* Software reboot */
348 /* Ethernet at SCC2 */
349 #define CONFIG_SCC2_ENET
351 #define CONFIG_ARTOS /* include ARTOS support */
353 /****************************************************************/
355 #define DSP_SIZE 0x00010000 /* 64K */
356 #define FPGA_SIZE 0x00010000 /* 64K */
358 #define DSP0_BASE 0xF1000000
359 #define DSP1_BASE (DSP0_BASE + DSP_SIZE)
360 #define FPGA_BASE (DSP1_BASE + DSP_SIZE)
362 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
364 #define ER_SIZE 0x00010000 /* 64K */
365 #define ER_BASE (FPGA_BASE + FPGA_SIZE)
367 #define NAND_SIZE 0x00010000 /* 64K */
368 #define NAND_BASE (ER_BASE + ER_SIZE)
372 /****************************************************************/
374 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
376 #define STATUS_LED_BIT 0x00000001 /* bit 31 */
377 #define STATUS_LED_PERIOD (CFG_HZ / 2)
378 #define STATUS_LED_STATE STATUS_LED_BLINKING
380 #define STATUS_LED_BIT1 0x00000002 /* bit 30 */
381 #define STATUS_LED_PERIOD1 (CFG_HZ / 2)
382 #define STATUS_LED_STATE1 STATUS_LED_OFF
384 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
385 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
389 /*****************************************************************************/
391 #define CFG_NAND_LEGACY
393 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
396 #define CFG_NAND_BASE NAND_BASE
397 #define CONFIG_MTD_NAND_ECC_JFFS2
399 #define CFG_MAX_NAND_DEVICE 1
401 #define SECTORSIZE 512
402 #define ADDR_COLUMN 1
404 #define ADDR_COLUMN_PAGE 3
405 #define NAND_ChipID_UNKNOWN 0x00
406 #define NAND_MAX_FLOORS 1
407 #define NAND_MAX_CHIPS 1
409 #define NAND_DISABLE_CE(nand) \
411 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
414 #define NAND_ENABLE_CE(nand) \
416 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
419 #define NAND_CTL_CLRALE(nandptr) \
421 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
424 #define NAND_CTL_SETALE(nandptr) \
426 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
429 #define NAND_CTL_CLRCLE(nandptr) \
431 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
434 #define NAND_CTL_SETCLE(nandptr) \
436 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
439 #define NAND_WAIT_READY(nand) \
441 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
445 #define WRITE_NAND_COMMAND(d, adr) \
447 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
450 #define WRITE_NAND_ADDRESS(d, adr) \
452 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
455 #define WRITE_NAND(d, adr) \
457 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
460 #define READ_NAND(adr) \
461 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
465 /*****************************************************************************/
469 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
473 /* last value written to the external register; we cannot read back */
474 extern unsigned int last_er_val;
476 /* led_id_t is unsigned long mask */
477 typedef unsigned int led_id_t;
479 static inline void __led_init(led_id_t mask, int state)
481 unsigned int new_er_val;
484 new_er_val = last_er_val & ~mask;
486 new_er_val = last_er_val | mask;
488 *(volatile unsigned int *)ER_BASE = new_er_val;
489 last_er_val = new_er_val;
492 static inline void __led_toggle(led_id_t mask)
494 unsigned int new_er_val;
496 new_er_val = last_er_val ^ mask;
497 *(volatile unsigned int *)ER_BASE = new_er_val;
498 last_er_val = new_er_val;
501 static inline void __led_set(led_id_t mask, int state)
503 unsigned int new_er_val;
506 new_er_val = last_er_val & ~mask;
508 new_er_val = last_er_val | mask;
510 *(volatile unsigned int *)ER_BASE = new_er_val;
511 last_er_val = new_er_val;
514 /* MAX3100 console */
515 #define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
516 #define MAX3100_SPI_RXD_BIT 0x00000008
518 #define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
519 #define MAX3100_SPI_TXD_BIT 0x00000004
521 #define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
522 #define MAX3100_SPI_CLK_BIT 0x00000002
524 #define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
525 #define MAX3100_CS_BIT 0x0010
531 /*************************************************************************************************/
533 #endif /* __CONFIG_H */