3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
21 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
22 #define CONFIG_OCRTC 1 /* ...on a OCRTC board */
24 #define CONFIG_SYS_TEXT_BASE 0xFFFD0000
26 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
28 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
30 #define CONFIG_BAUDRATE 9600
31 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
33 #undef CONFIG_BOOTARGS
34 #define CONFIG_BOOTCOMMAND "go fff00100"
36 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
37 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
39 #define CONFIG_PPC4xx_EMAC
40 #define CONFIG_MII 1 /* MII PHY management */
41 #define CONFIG_PHY_ADDR 0 /* PHY address */
42 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
48 #define CONFIG_BOOTP_BOOTFILESIZE
49 #define CONFIG_BOOTP_BOOTPATH
50 #define CONFIG_BOOTP_GATEWAY
51 #define CONFIG_BOOTP_HOSTNAME
55 * Command line configuration.
57 #include <config_cmd_default.h>
59 #define CONFIG_CMD_PCI
60 #define CONFIG_CMD_IRQ
61 #define CONFIG_CMD_ASKENV
62 #define CONFIG_CMD_ELF
63 #define CONFIG_CMD_BSP
64 #define CONFIG_CMD_EEPROM
67 #define CONFIG_MAC_PARTITION
68 #define CONFIG_DOS_PARTITION
70 #undef CONFIG_WATCHDOG /* watchdog disabled */
72 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
75 * Miscellaneous configurable options
77 #define CONFIG_SYS_LONGHELP /* undef to save memory */
78 #if defined(CONFIG_CMD_KGDB)
79 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
81 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
84 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
85 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
87 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
89 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
92 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
93 #define CONFIG_SYS_NS16550
94 #define CONFIG_SYS_NS16550_SERIAL
95 #define CONFIG_SYS_NS16550_REG_SIZE 1
96 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
98 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
99 #define CONFIG_SYS_BASE_BAUD 691200
101 /* The following table includes the supported baudrates */
102 #define CONFIG_SYS_BAUDRATE_TABLE \
103 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
104 57600, 115200, 230400, 460800, 921600 }
106 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
107 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
109 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
111 /*-----------------------------------------------------------------------
113 *-----------------------------------------------------------------------
115 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
116 #define PCI_HOST_FORCE 1 /* configure as pci host */
117 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
119 #define CONFIG_PCI /* include pci support */
120 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
121 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
122 #define CONFIG_PCI_PNP /* do pci plug-and-play */
123 /* resource configuration */
125 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
127 #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
129 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
130 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */
131 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
132 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
133 #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
134 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
135 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
136 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
137 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
139 /*-----------------------------------------------------------------------
140 * Start addresses for the final memory configuration
141 * (Set up by the startup code)
142 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
144 #define CONFIG_SYS_SDRAM_BASE 0x00000000
145 #define CONFIG_SYS_FLASH_BASE 0xFFFD0000
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
147 #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
148 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
151 * For booting Linux, the board info and command line data
152 * have to be in the first 8 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization.
155 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
156 /*-----------------------------------------------------------------------
159 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
160 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
162 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
163 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
165 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
166 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
167 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
169 * The following defines are added for buggy IOP480 byte interface.
170 * All other boards should use the standard values (CPCI405 etc.)
172 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
173 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
174 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
176 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
178 #if 0 /* Use NVRAM for environment variables */
179 /*-----------------------------------------------------------------------
182 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
183 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
184 #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
185 #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
186 #define CONFIG_ENV_ADDR \
187 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
188 #define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
190 #else /* Use EEPROM for environment variables */
192 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
193 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
194 #define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
195 /* total size of a CAT24WC08 is 1024 bytes */
198 /*-----------------------------------------------------------------------
199 * I2C EEPROM (CAT24WC08) for environment
201 #define CONFIG_SYS_I2C
202 #define CONFIG_SYS_I2C_PPC4XX
203 #define CONFIG_SYS_I2C_PPC4XX_CH0
204 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
205 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
209 /* mask of address bits that overflow into the "EEPROM chip address" */
210 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
212 /* 16 byte page write mode using*/
213 /* last 4 bits of the address */
214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
217 * Init Memory Controller:
219 * BR0/1 and OR0/1 (FLASH)
222 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
223 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
225 /*-----------------------------------------------------------------------
226 * External Bus Controller (EBC) Setup
229 /* Memory Bank 0 (Flash Bank 0) initialization */
230 #define CONFIG_SYS_EBC_PB0AP 0x92015480
231 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
233 /* Memory Bank 1 (Flash Bank 1) initialization */
234 #define CONFIG_SYS_EBC_PB1AP 0x92015480
235 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
237 /* Memory Bank 2 (PLD - FPGA-boot) initialization */
238 #define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
239 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
240 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
242 /* Memory Bank 3 (PLD - OSL) initialization */
243 #define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
244 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
245 #define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
247 /* Memory Bank 4 (Spartan2 1) initialization */
248 #define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
249 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
250 #define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
252 /* Memory Bank 5 (Spartan2 2) initialization */
253 #define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
254 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
255 #define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
257 /* Memory Bank 6 (Virtex 1) initialization */
258 #define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
259 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
260 #define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
262 /* Memory Bank 7 (Virtex 2) initialization */
263 #define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
264 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
265 #define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
268 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
270 /*-----------------------------------------------------------------------
271 * Definitions for initial stack pointer and data area (in DPRAM)
274 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
275 #define CONFIG_SYS_TEMP_STACK_OCM 1
277 /* On Chip Memory location */
278 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
279 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
281 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
282 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
283 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
284 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
286 #endif /* __CONFIG_H */