2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P010 RDB board configuration file
31 #define CONFIG_PHYS_64BIT
35 #define CONFIG_E500 /* BOOKE e500 family */
36 #include <asm/config_mpc85xx.h>
37 #define CONFIG_NAND_FSL_IFC
40 #define CONFIG_RAMBOOT_SDCARD
41 #define CONFIG_SYS_TEXT_BASE 0x11000000
42 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
45 #ifdef CONFIG_SPIFLASH
46 #define CONFIG_RAMBOOT_SPIFLASH
47 #define CONFIG_SYS_TEXT_BASE 0x11000000
48 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
53 #define CONFIG_SPL_INIT_MINIMAL
54 #define CONFIG_SPL_SERIAL_SUPPORT
55 #define CONFIG_SPL_NAND_SUPPORT
56 #define CONFIG_SPL_NAND_MINIMAL
57 #define CONFIG_SPL_FLUSH_IMAGE
58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
60 #define CONFIG_SYS_TEXT_BASE 0x00201000
61 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
62 #define CONFIG_SPL_MAX_SIZE 8192
63 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
64 #define CONFIG_SPL_RELOC_STACK 0x00100000
65 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
66 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
67 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
68 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
69 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
73 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
74 #define CONFIG_RAMBOOT_NAND
75 #define CONFIG_SYS_TEXT_BASE 0x11000000
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
79 #ifndef CONFIG_SYS_TEXT_BASE
80 #define CONFIG_SYS_TEXT_BASE 0xeff80000
83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
84 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
87 #ifdef CONFIG_SPL_BUILD
88 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
93 /* High Level Configuration Options */
94 #define CONFIG_BOOKE /* BOOKE */
95 #define CONFIG_E500 /* BOOKE e500 family */
96 #define CONFIG_MPC85xx
97 #define CONFIG_FSL_IFC /* Enable IFC Support */
98 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
100 #define CONFIG_PCI /* Enable PCI/PCIE */
101 #if defined(CONFIG_PCI)
102 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
103 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
104 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
105 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
106 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
107 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
109 #define CONFIG_CMD_NET
110 #define CONFIG_CMD_PCI
112 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
116 * Memory space is mapped 1-1, but I/O space must start from 0.
118 /* controller 1, Slot 1, tgtid 1, Base address a000 */
119 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
120 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
121 #ifdef CONFIG_PHYS_64BIT
122 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
123 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
125 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
126 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
128 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
129 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
130 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
131 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
135 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
138 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
139 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
140 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
141 #ifdef CONFIG_PHYS_64BIT
142 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
143 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
145 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
146 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
148 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
149 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
150 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
151 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
152 #ifdef CONFIG_PHYS_64BIT
153 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
155 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
158 #define CONFIG_PCI_PNP /* do pci plug-and-play */
160 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
161 #define CONFIG_DOS_PARTITION
164 #define CONFIG_FSL_LAW /* Use common FSL init code */
165 #define CONFIG_TSEC_ENET
166 #define CONFIG_ENV_OVERWRITE
168 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
169 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
171 #ifndef CONFIG_SDCARD
172 #define CONFIG_MISC_INIT_R
175 #define CONFIG_HWCONFIG
177 * These can be toggled for performance analysis, otherwise use default.
179 #define CONFIG_L2_CACHE /* toggle L2 cache */
180 #define CONFIG_BTB /* toggle branch predition */
182 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
184 #define CONFIG_ENABLE_36BIT_PHYS
186 #ifdef CONFIG_PHYS_64BIT
187 #define CONFIG_ADDR_MAP 1
188 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
191 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
192 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
193 #define CONFIG_PANIC_HANG /* do not reset board on panic */
196 #define CONFIG_FSL_DDR3
197 #define CONFIG_SYS_DDR_RAW_TIMING
198 #define CONFIG_DDR_SPD
199 #define CONFIG_SYS_SPD_BUS_NUM 1
200 #define SPD_EEPROM_ADDRESS 0x52
202 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
205 extern unsigned long get_sdram_size(void);
207 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
211 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
212 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
214 /* DDR3 Controller Settings */
215 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
216 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
217 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
218 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
219 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
220 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
221 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
223 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
224 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
225 #define CONFIG_SYS_DDR_RCW_1 0x00000000
226 #define CONFIG_SYS_DDR_RCW_2 0x00000000
227 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
228 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010
229 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
230 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
232 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
233 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
234 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
235 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
236 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
237 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
238 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
239 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
240 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
242 /* settings for DDR3 at 667MT/s */
243 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
244 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
245 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
246 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
247 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
248 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
249 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
250 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
251 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
253 #define CONFIG_SYS_CCSRBAR 0xffe00000
254 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
256 /* Don't relocate CCSRBAR while in NAND_SPL */
257 #ifdef CONFIG_SPL_BUILD
258 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
264 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
265 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
266 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
268 * Localbus non-cacheable
269 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
270 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
271 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
272 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
275 /* In case of SD card boot, IFC interface is not available because of muxing */
277 #define CONFIG_SYS_NO_FLASH
282 /* NOR Flash on IFC */
283 #ifdef CONFIG_SPL_BUILD
284 #define CONFIG_SYS_NO_FLASH
287 #define CONFIG_SYS_FLASH_BASE 0xee000000
288 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
290 #ifdef CONFIG_PHYS_64BIT
291 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
293 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
296 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
297 CSPR_PORT_SIZE_16 | \
300 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
301 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
302 /* NOR Flash Timing Params */
303 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
304 FTIM0_NOR_TEADC(0x5) | \
306 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
307 FTIM1_NOR_TRAD_NOR(0x0f)
308 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
309 FTIM2_NOR_TCH(0x4) | \
311 #define CONFIG_SYS_NOR_FTIM3 0x0
313 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
314 #define CONFIG_SYS_FLASH_QUIET_TEST
315 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
316 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
318 #undef CONFIG_SYS_FLASH_CHECKSUM
319 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
320 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
322 /* CFI for NOR Flash */
323 #define CONFIG_FLASH_CFI_DRIVER
324 #define CONFIG_SYS_FLASH_CFI
325 #define CONFIG_SYS_FLASH_EMPTY_INFO
326 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
328 /* NAND Flash on IFC */
329 #define CONFIG_SYS_NAND_BASE 0xff800000
330 #ifdef CONFIG_PHYS_64BIT
331 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
333 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
336 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
341 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
342 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
343 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
344 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
345 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
346 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
347 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
349 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
350 #define CONFIG_SYS_MAX_NAND_DEVICE 1
351 #define CONFIG_MTD_NAND_VERIFY_WRITE
352 #define CONFIG_CMD_NAND
353 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
355 /* NAND Flash Timing Params */
356 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
357 FTIM0_NAND_TWP(0x0C) | \
358 FTIM0_NAND_TWCHT(0x04) | \
360 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
361 FTIM1_NAND_TWBE(0x1d) | \
362 FTIM1_NAND_TRR(0x07) | \
364 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
365 FTIM2_NAND_TREH(0x05) | \
366 FTIM2_NAND_TWHRE(0x0f)
367 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
369 #define CONFIG_SYS_NAND_DDR_LAW 11
371 /* Set up IFC registers for boot location NOR/NAND */
372 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
388 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
389 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
390 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
391 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
392 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
393 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
394 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
395 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
396 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
397 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
398 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
399 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
400 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
401 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
405 #define CONFIG_SYS_CPLD_BASE 0xffb00000
407 #ifdef CONFIG_PHYS_64BIT
408 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
410 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
413 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
417 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
418 #define CONFIG_SYS_CSOR3 0x0
419 /* CPLD Timing parameters for IFC CS3 */
420 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
421 FTIM0_GPCM_TEADC(0x0e) | \
422 FTIM0_GPCM_TEAHC(0x0e))
423 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
424 FTIM1_GPCM_TRAD(0x1f))
425 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
426 FTIM2_GPCM_TCH(0x0) | \
427 FTIM2_GPCM_TWP(0x1f))
428 #define CONFIG_SYS_CS3_FTIM3 0x0
429 #endif /* CONFIG_SDCARD */
431 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
432 #define CONFIG_SYS_RAMBOOT
433 #define CONFIG_SYS_EXTRA_ENV_RELOC
435 #undef CONFIG_SYS_RAMBOOT
438 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
439 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
440 && !defined(CONFIG_SECURE_BOOT)
441 #define CONFIG_A003399_NOR_WORKAROUND
445 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
446 #define CONFIG_BOARD_EARLY_INIT_R
448 #define CONFIG_SYS_INIT_RAM_LOCK
449 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
450 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
452 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
453 - GENERATED_GBL_DATA_SIZE)
454 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
456 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
457 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
460 #define CONFIG_CONS_INDEX 1
461 #undef CONFIG_SERIAL_SOFTWARE_FIFO
462 #define CONFIG_SYS_NS16550
463 #define CONFIG_SYS_NS16550_SERIAL
464 #define CONFIG_SYS_NS16550_REG_SIZE 1
465 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
466 #ifdef CONFIG_SPL_BUILD
467 #define CONFIG_NS16550_MIN_FUNCTIONS
470 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
472 #define CONFIG_SYS_BAUDRATE_TABLE \
473 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
475 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
476 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
478 /* Use the HUSH parser */
479 #define CONFIG_SYS_HUSH_PARSER
482 * Pass open firmware flat tree
484 #define CONFIG_OF_LIBFDT
485 #define CONFIG_OF_BOARD_SETUP
486 #define CONFIG_OF_STDOUT_VIA_ALIAS
488 /* new uImage format support */
490 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
493 #define CONFIG_SYS_I2C
494 #define CONFIG_SYS_I2C_FSL
495 #define CONFIG_SYS_FSL_I2C_SPEED 400000
496 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
497 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
498 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
499 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
500 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
503 #undef CONFIG_ID_EEPROM
504 /* enable read and write access to EEPROM */
505 #define CONFIG_CMD_EEPROM
506 #define CONFIG_SYS_I2C_MULTI_EEPROMS
507 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
508 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
509 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
512 #define CONFIG_RTC_PT7C4338
513 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
515 #define CONFIG_CMD_I2C
518 * SPI interface will not be available in case of NAND boot SPI CS0 will be
521 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
522 /* eSPI - Enhanced SPI */
523 #define CONFIG_FSL_ESPI
524 #define CONFIG_SPI_FLASH
525 #define CONFIG_SPI_FLASH_SPANSION
526 #define CONFIG_CMD_SF
527 #define CONFIG_SF_DEFAULT_SPEED 10000000
528 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
531 #if defined(CONFIG_TSEC_ENET)
532 #define CONFIG_MII /* MII PHY management */
533 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
534 #define CONFIG_TSEC1 1
535 #define CONFIG_TSEC1_NAME "eTSEC1"
536 #define CONFIG_TSEC2 1
537 #define CONFIG_TSEC2_NAME "eTSEC2"
538 #define CONFIG_TSEC3 1
539 #define CONFIG_TSEC3_NAME "eTSEC3"
541 #define TSEC1_PHY_ADDR 1
542 #define TSEC2_PHY_ADDR 0
543 #define TSEC3_PHY_ADDR 2
545 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
546 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
547 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
549 #define TSEC1_PHYIDX 0
550 #define TSEC2_PHYIDX 0
551 #define TSEC3_PHYIDX 0
553 #define CONFIG_ETHPRIME "eTSEC1"
555 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
557 /* TBI PHY configuration for SGMII mode */
558 #define CONFIG_TSEC_TBICR_SETTINGS ( \
560 | TBICR_ANEG_ENABLE \
561 | TBICR_FULL_DUPLEX \
565 #endif /* CONFIG_TSEC_ENET */
569 #define CONFIG_FSL_SATA
570 #define CONFIG_FSL_SATA_V2
571 #define CONFIG_LIBATA
573 #ifdef CONFIG_FSL_SATA
574 #define CONFIG_SYS_SATA_MAX_DEVICE 2
576 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
577 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
579 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
580 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
582 #define CONFIG_CMD_SATA
584 #endif /* #ifdef CONFIG_FSL_SATA */
586 /* SD interface will only be available in case of SD boot */
589 #define CONFIG_DEF_HWCONFIG esdhc
593 #define CONFIG_CMD_MMC
594 #define CONFIG_DOS_PARTITION
595 #define CONFIG_FSL_ESDHC
596 #define CONFIG_GENERIC_MMC
597 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
600 #define CONFIG_HAS_FSL_DR_USB
602 #if defined(CONFIG_HAS_FSL_DR_USB)
603 #define CONFIG_USB_EHCI
605 #ifdef CONFIG_USB_EHCI
606 #define CONFIG_CMD_USB
607 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
608 #define CONFIG_USB_EHCI_FSL
609 #define CONFIG_USB_STORAGE
616 #if defined(CONFIG_RAMBOOT_SDCARD)
617 #define CONFIG_ENV_IS_IN_MMC
618 #define CONFIG_FSL_FIXED_MMC_LOCATION
619 #define CONFIG_SYS_MMC_ENV_DEV 0
620 #define CONFIG_ENV_SIZE 0x2000
621 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
622 #define CONFIG_ENV_IS_IN_SPI_FLASH
623 #define CONFIG_ENV_SPI_BUS 0
624 #define CONFIG_ENV_SPI_CS 0
625 #define CONFIG_ENV_SPI_MAX_HZ 10000000
626 #define CONFIG_ENV_SPI_MODE 0
627 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
628 #define CONFIG_ENV_SECT_SIZE 0x10000
629 #define CONFIG_ENV_SIZE 0x2000
630 #elif defined(CONFIG_NAND)
631 #define CONFIG_ENV_IS_IN_NAND
632 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
633 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
634 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
635 #elif defined(CONFIG_SYS_RAMBOOT)
636 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
637 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
638 #define CONFIG_ENV_SIZE 0x2000
640 #define CONFIG_ENV_IS_IN_FLASH
641 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
642 #define CONFIG_ENV_ADDR 0xfff80000
644 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
646 #define CONFIG_ENV_SIZE 0x2000
647 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
650 #define CONFIG_LOADS_ECHO /* echo on for serial download */
651 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
654 * Command line configuration.
656 #include <config_cmd_default.h>
658 #define CONFIG_CMD_DATE
659 #define CONFIG_CMD_ERRATA
660 #define CONFIG_CMD_ELF
661 #define CONFIG_CMD_IRQ
662 #define CONFIG_CMD_MII
663 #define CONFIG_CMD_PING
664 #define CONFIG_CMD_SETEXPR
665 #define CONFIG_CMD_REGINFO
667 #undef CONFIG_WATCHDOG /* watchdog disabled */
669 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
670 || defined(CONFIG_FSL_SATA)
671 #define CONFIG_CMD_EXT2
672 #define CONFIG_CMD_FAT
673 #define CONFIG_DOS_PARTITION
677 * Miscellaneous configurable options
679 #define CONFIG_SYS_LONGHELP /* undef to save memory */
680 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
681 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
682 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
683 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
685 #if defined(CONFIG_CMD_KGDB)
686 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
688 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
690 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
691 /* Print Buffer Size */
692 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
693 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
694 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
697 * Internal Definitions
701 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
702 #define BOOTFLAG_WARM 0x02 /* Software reboot */
705 * For booting Linux, the board info and command line data
706 * have to be in the first 64 MB of memory, since this is
707 * the maximum mapped by the Linux kernel during initialization.
709 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
710 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
712 #if defined(CONFIG_CMD_KGDB)
713 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
714 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
718 * Environment Configuration
721 #if defined(CONFIG_TSEC_ENET)
722 #define CONFIG_HAS_ETH0
723 #define CONFIG_HAS_ETH1
724 #define CONFIG_HAS_ETH2
727 #define CONFIG_HOSTNAME P1010RDB
728 #define CONFIG_ROOTPATH "/opt/nfsroot"
729 #define CONFIG_BOOTFILE "uImage"
730 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
732 /* default location for tftp and bootm */
733 #define CONFIG_LOADADDR 1000000
735 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
736 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
738 #define CONFIG_BAUDRATE 115200
740 #define CONFIG_EXTRA_ENV_SETTINGS \
741 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
743 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
744 "loadaddr=1000000\0" \
745 "consoledev=ttyS0\0" \
746 "ramdiskaddr=2000000\0" \
747 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
749 "fdtfile=p1010rdb.dtb\0" \
751 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
752 "othbootargs=ramdisk_size=600000\0" \
753 "usbfatboot=setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs; " \
756 "fatload usb 0:2 $loadaddr $bootfile;" \
757 "fatload usb 0:2 $fdtaddr $fdtfile;" \
758 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
759 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
760 "usbext2boot=setenv bootargs root=/dev/ram rw " \
761 "console=$consoledev,$baudrate $othbootargs; " \
763 "ext2load usb 0:4 $loadaddr $bootfile;" \
764 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
765 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
766 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
768 #define CONFIG_RAMBOOTCOMMAND \
769 "setenv bootargs root=/dev/ram rw " \
770 "console=$consoledev,$baudrate $othbootargs; " \
771 "tftp $ramdiskaddr $ramdiskfile;" \
772 "tftp $loadaddr $bootfile;" \
773 "tftp $fdtaddr $fdtfile;" \
774 "bootm $loadaddr $ramdiskaddr $fdtaddr"
776 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
778 #ifdef CONFIG_SECURE_BOOT
779 #include <asm/fsl_secure_boot.h>
782 #endif /* __CONFIG_H */