2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <b25806@freescale.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * p1023rds board configuration file
34 #define CONFIG_NAND_U_BOOT
35 #define CONFIG_RAMBOOT_NAND
38 #ifdef CONFIG_NAND_U_BOOT
39 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
40 #define CONFIG_SYS_TEXT_BASE 0x11001000
42 #ifdef CONFIG_NAND_SPL
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
45 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
47 #endif /* CONFIG_NAND_SPL */
50 #ifndef CONFIG_SYS_TEXT_BASE
51 #define CONFIG_SYS_TEXT_BASE 0xeff80000
54 #ifndef CONFIG_SYS_MONITOR_BASE
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 /* High Level Configuration Options */
63 #define CONFIG_BOOKE /* BOOKE */
64 #define CONFIG_E500 /* BOOKE e500 family */
65 #define CONFIG_MPC85xx
67 #define CONFIG_P1023RDS
68 #define CONFIG_MP /* support multiple processors */
70 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
71 #define CONFIG_PCI /* Enable PCI/PCIE */
72 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
73 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
74 #define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
75 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
76 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
77 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
78 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
79 #define CONFIG_FSL_LAW /* Use common FSL init code */
82 extern unsigned long get_clock_freq(void);
85 #define CONFIG_SYS_CLK_FREQ 66666666
86 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
89 * These can be toggled for performance analysis, otherwise use default.
91 #define CONFIG_L2_CACHE /* toggle L2 cache */
92 #define CONFIG_BTB /* toggle branch predition */
93 #define CONFIG_HWCONFIG
95 #define CONFIG_ENABLE_36BIT_PHYS
97 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
98 #define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
99 #define CONFIG_PANIC_HANG /* do not reset board on panic */
101 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
102 addresses in the LBC */
105 #define CONFIG_VERY_BIG_RAM
107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
108 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
114 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
116 /* These are used when DDR doesn't use SPD. */
117 #define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
119 /* Default settings for "stable" mode */
120 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
121 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
123 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
124 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
125 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
126 #define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
127 #define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
128 #define CONFIG_SYS_DDR_MODE_1 0x00441210
129 #define CONFIG_SYS_DDR_MODE_2 0x00000000
130 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
131 #define CONFIG_SYS_DDR_INTERVAL 0x0A280100
132 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
133 #define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
134 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
135 #define CONFIG_SYS_DDR_TIMING_5 0x01401400
136 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
137 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
138 #define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
139 #define CONFIG_SYS_DDR_CONTROL2 0x24401010
140 #define CONFIG_SYS_DDR_CDR1 0x00000000
141 #define CONFIG_SYS_DDR_CDR2 0x00000000
143 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
144 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
145 #define CONFIG_SYS_DDR_SBE 0x00000000
147 /* Settings that differ for "performance" mode */
148 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
149 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
150 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
151 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
152 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
153 /* Type = DDR3: cs0-cs1 interleaving */
154 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
155 #define CONFIG_SYS_DDR_CDR_1 0x00000000
156 #define CONFIG_SYS_DDR_CDR_2 0x00000000
162 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
163 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
164 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
165 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
167 * Localbus non-cacheable
168 * 0xe000_0000 0xe003_ffff BCSR 256K BCSR
169 * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
170 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
171 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
172 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
173 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
177 * Local Bus Definitions
179 #define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
180 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
183 #define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
185 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
187 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
189 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
191 #define CONFIG_FLASH_CFI_DRIVER
192 #define CONFIG_SYS_FLASH_CFI
193 #define CONFIG_SYS_FLASH_EMPTY_INFO
195 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
196 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
200 #define CONFIG_SYS_NO_FLASH
203 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
204 #define CONFIG_SYS_RAMBOOT
207 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
208 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
210 #define CONFIG_SYS_INIT_RAM_LOCK
211 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
212 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
214 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
215 #define CONFIG_SYS_GBL_DATA_OFFSET \
216 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
219 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
220 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
222 #ifndef CONFIG_NAND_SPL
223 #define CONFIG_SYS_NAND_BASE 0xffa00000
224 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
226 #define CONFIG_SYS_NAND_BASE 0xfff00000
227 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
230 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
231 #define CONFIG_SYS_MAX_NAND_DEVICE 1
232 #define CONFIG_MTD_NAND_VERIFY_WRITE
233 #define CONFIG_CMD_NAND
234 #define CONFIG_NAND_FSL_ELBC
235 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
237 /* NAND boot: 4K NAND loader config */
238 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
239 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
240 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
241 #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
242 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
243 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
244 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
246 /* NAND flash config */
247 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
248 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
249 | BR_PS_8 /* Port Size = 8bit */ \
250 | BR_MS_FCM /* MSEL = FCM */ \
252 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
260 #ifdef CONFIG_RAMBOOT_NAND
261 /* NAND Base Address */
262 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
263 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
264 /* chip select 1 - BCSR */
265 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
266 | BR_MS_GPCM | BR_PS_8 | BR_V)
267 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
268 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
271 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
272 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
273 /* chip select 1 - BCSR */
274 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
275 | BR_MS_GPCM | BR_PS_8 | BR_V)
276 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
277 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
285 #define CONFIG_CONS_INDEX 1
286 #undef CONFIG_SERIAL_SOFTWARE_FIFO
287 #define CONFIG_SYS_NS16550
288 #define CONFIG_SYS_NS16550_SERIAL
289 #define CONFIG_SYS_NS16550_REG_SIZE 1
290 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
291 #ifdef CONFIG_NAND_SPL
292 #define CONFIG_NS16550_MIN_FUNCTIONS
295 #define CONFIG_SYS_BAUDRATE_TABLE \
296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
301 /* Use the HUSH parser */
302 #define CONFIG_SYS_HUSH_PARSER
305 * Pass open firmware flat tree
307 #define CONFIG_OF_LIBFDT
308 #define CONFIG_OF_BOARD_SETUP
309 #define CONFIG_OF_STDOUT_VIA_ALIAS
311 /* new uImage format support */
313 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
316 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
317 #define CONFIG_HARD_I2C /* I2C with hardware support */
318 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
319 #define CONFIG_I2C_MULTI_BUS
320 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
321 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
322 #define CONFIG_SYS_I2C_SLAVE 0x7F
323 #define CONFIG_SYS_I2C_OFFSET 0x3000
324 #define CONFIG_SYS_I2C2_OFFSET 0x3100
329 #define CONFIG_ID_EEPROM
330 #ifdef CONFIG_ID_EEPROM
331 #define CONFIG_SYS_I2C_EEPROM_NXID
333 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
335 #define CONFIG_SYS_EEPROM_BUS_NUM 0
337 #define CONFIG_CMD_I2C
340 * eSPI - Enhanced SPI
342 #define CONFIG_SPI_FLASH
343 #define CONFIG_SPI_FLASH_ATMEL
345 #define CONFIG_HARD_SPI
346 #define CONFIG_FSL_ESPI
348 #define CONFIG_CMD_SF
349 #define CONFIG_SF_DEFAULT_SPEED 10000000
350 #define CONFIG_SF_DEFAULT_MODE 0
354 * Memory space is mapped 1-1, but I/O space must start from 0.
357 /* controller 3, Slot 1, tgtid 3, Base address b000 */
358 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
359 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
360 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
361 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
362 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
363 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
364 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
365 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
366 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
368 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
369 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
370 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
371 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
372 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
373 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
374 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
375 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
376 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
377 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
379 /* controller 1, Slot 2, tgtid 1, Base address a000 */
380 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
381 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
382 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
383 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
384 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
385 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
386 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
387 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
388 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
390 #if defined(CONFIG_PCI)
391 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
392 #define CONFIG_PCI_PNP /* do pci plug-and-play */
393 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
394 #endif /* CONFIG_PCI */
399 #define CONFIG_ENV_OVERWRITE
401 #if defined(CONFIG_SYS_RAMBOOT)
402 #if defined(CONFIG_RAMBOOT_NAND)
403 #define CONFIG_ENV_IS_IN_NAND
404 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
405 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
407 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
408 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
409 #define CONFIG_ENV_SIZE 0x2000
412 #define CONFIG_ENV_IS_IN_FLASH
413 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
414 #define CONFIG_ENV_ADDR 0xfff80000
416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
418 #define CONFIG_ENV_SIZE 0x2000
419 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
422 #define CONFIG_LOADS_ECHO /* echo on for serial download */
423 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
426 * Command line configuration.
428 #include <config_cmd_default.h>
430 #define CONFIG_CMD_IRQ
431 #define CONFIG_CMD_PING
432 #define CONFIG_CMD_MII
433 #define CONFIG_CMD_ELF
434 #define CONFIG_CMD_SETEXPR
435 #define CONFIG_CMD_REGINFO
437 #if defined(CONFIG_PCI)
438 #define CONFIG_CMD_PCI
439 #define CONFIG_CMD_NET
445 #define CONFIG_HAS_FSL_DR_USB
446 #ifdef CONFIG_HAS_FSL_DR_USB
447 #define CONFIG_USB_EHCI
449 #ifdef CONFIG_USB_EHCI
450 #define CONFIG_CMD_USB
451 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
452 #define CONFIG_USB_EHCI_FSL
453 #define CONFIG_USB_STORAGE
454 #define CONFIG_CMD_FAT
455 #define CONFIG_CMD_EXT2
456 #define CONFIG_CMD_FAT
457 #define CONFIG_DOS_PARTITION
462 * Miscellaneous configurable options
464 #define CONFIG_SYS_LONGHELP /* undef to save memory */
465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
466 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
467 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
468 #if defined(CONFIG_CMD_KGDB)
469 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
471 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
473 /* Print Buffer Size */
474 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
475 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
476 /* Boot Argument Buffer Size */
477 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
478 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
481 * For booting Linux, the board info and command line data
482 * have to be in the first 16 MB of memory, since this is
483 * the maximum mapped by the Linux kernel during initialization.
485 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
486 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
488 #if defined(CONFIG_CMD_KGDB)
489 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
490 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
494 * Environment Configuration
496 #define CONFIG_BOOTFILE "uImage"
497 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
499 /* default location for tftp and bootm */
500 #define CONFIG_LOADADDR 1000000
502 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
504 #define CONFIG_BAUDRATE 115200
507 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
508 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
509 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
510 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
511 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
512 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
513 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
516 #define CONFIG_SYS_DPAA_FMAN
517 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
519 #ifdef CONFIG_SYS_DPAA_FMAN
520 #define CONFIG_FMAN_ENET
521 #define CONFIG_PHY_MARVELL
525 /* Default address of microcode for the Linux Fman driver */
526 /* QE microcode/firmware address */
527 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
530 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
531 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000
533 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
534 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
536 #ifdef CONFIG_FMAN_ENET
537 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
538 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
540 #define CONFIG_SYS_TBIPA_VALUE 8
541 #define CONFIG_MII /* MII PHY management */
542 #define CONFIG_ETHPRIME "FM1@DTSEC1"
545 #define CONFIG_EXTRA_ENV_SETTINGS \
546 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
548 #endif /* __CONFIG_H */