2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
33 #ifdef CONFIG_P1011RDB
36 #ifdef CONFIG_P1020RDB
39 #ifdef CONFIG_P2010RDB
42 #ifdef CONFIG_P2020RDB
47 #define CONFIG_NAND_U_BOOT 1
48 #define CONFIG_RAMBOOT_NAND 1
49 #ifdef CONFIG_NAND_SPL
50 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
53 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
54 #endif /* CONFIG_NAND_SPL */
58 #define CONFIG_RAMBOOT_SDCARD 1
59 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
63 #ifdef CONFIG_SPIFLASH
64 #define CONFIG_RAMBOOT_SPIFLASH 1
65 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
66 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
69 #ifndef CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_TEXT_BASE 0xeff80000
73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
77 #ifndef CONFIG_SYS_MONITOR_BASE
78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
81 /* High Level Configuration Options */
82 #define CONFIG_BOOKE 1 /* BOOKE */
83 #define CONFIG_E500 1 /* BOOKE e500 family */
84 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
85 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
86 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
87 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
88 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
89 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
90 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
91 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
92 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
93 #define CONFIG_TSEC_ENET /* tsec ethernet support */
94 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
98 extern unsigned long get_board_sys_clk(unsigned long dummy);
100 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
103 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
107 #define CONFIG_HWCONFIG
110 * These can be toggled for performance analysis, otherwise use default.
112 #define CONFIG_L2_CACHE /* toggle L2 cache */
113 #define CONFIG_BTB /* toggle branch predition */
115 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
117 #define CONFIG_ENABLE_36BIT_PHYS 1
119 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
121 #define CONFIG_PANIC_HANG /* do not reset board on panic */
124 * Config the L2 Cache as L2 SRAM
126 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
127 #ifdef CONFIG_PHYS_64BIT
128 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
130 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
132 #define CONFIG_SYS_L2_SIZE (512 << 10)
133 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
136 * Base addresses -- Note these are effective addresses where the
137 * actual resources get mapped (not physical addresses)
139 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
140 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
142 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
143 /* CONFIG_SYS_IMMR */
145 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
146 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
152 #define CONFIG_FSL_DDR2
153 #undef CONFIG_FSL_DDR_INTERACTIVE
154 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
156 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
158 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
162 #define CONFIG_NUM_DDR_CONTROLLERS 1
163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
164 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
166 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
167 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
168 #define CONFIG_SYS_DDR_SBE 0x00FF0000
173 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
174 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
175 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
177 * Localbus cacheable (TBD)
178 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
180 * Localbus non-cacheable
181 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
182 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
183 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
184 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
185 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
189 * Local Bus Definitions
191 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
193 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
195 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
197 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
199 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
200 #define CONFIG_SYS_FLASH_QUIET_TEST
201 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
203 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
205 #undef CONFIG_SYS_FLASH_CHECKSUM
206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
209 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
210 defined(CONFIG_RAMBOOT_SPIFLASH)
211 #define CONFIG_SYS_RAMBOOT
212 #define CONFIG_SYS_EXTRA_ENV_RELOC
214 #undef CONFIG_SYS_RAMBOOT
217 #define CONFIG_FLASH_CFI_DRIVER
218 #define CONFIG_SYS_FLASH_CFI
219 #define CONFIG_SYS_FLASH_EMPTY_INFO
220 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
222 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
223 #define CONFIG_HWCONFIG
225 #define CONFIG_SYS_INIT_RAM_LOCK 1
226 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
227 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
229 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
230 - GENERATED_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
234 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
236 #ifndef CONFIG_NAND_SPL
237 #define CONFIG_SYS_NAND_BASE 0xffa00000
239 #define CONFIG_SYS_NAND_BASE 0xfff00000
241 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
242 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
243 #define CONFIG_SYS_MAX_NAND_DEVICE 1
244 #define NAND_MAX_CHIPS 1
245 #define CONFIG_MTD_NAND_VERIFY_WRITE
246 #define CONFIG_CMD_NAND 1
247 #define CONFIG_NAND_FSL_ELBC 1
248 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
250 /* NAND boot: 4K NAND loader config */
251 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
252 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
253 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
254 #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
255 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
256 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
257 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
259 /* NAND flash config */
260 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
261 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
262 | BR_PS_8 /* Port Size = 8 bit */ \
263 | BR_MS_FCM /* MSEL = FCM */ \
266 #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
274 #ifdef CONFIG_RAMBOOT_NAND
275 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
276 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
277 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
278 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
280 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
281 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
282 #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
283 #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
286 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
288 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
290 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
291 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
292 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
293 OR_GPCM_EHTR | OR_GPCM_EAD)
295 /* Serial Port - controlled on board with jumper J8
299 #define CONFIG_CONS_INDEX 1
300 #define CONFIG_SYS_NS16550
301 #define CONFIG_SYS_NS16550_SERIAL
302 #define CONFIG_SYS_NS16550_REG_SIZE 1
303 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
304 #ifdef CONFIG_NAND_SPL
305 #define CONFIG_NS16550_MIN_FUNCTIONS
308 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
309 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
311 #define CONFIG_SYS_BAUDRATE_TABLE \
312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
317 /* Use the HUSH parser */
318 #define CONFIG_SYS_HUSH_PARSER
319 #ifdef CONFIG_SYS_HUSH_PARSER
320 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
324 * Pass open firmware flat tree
326 #define CONFIG_OF_LIBFDT 1
327 #define CONFIG_OF_BOARD_SETUP 1
328 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
330 /* new uImage format support */
332 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
335 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
336 #define CONFIG_HARD_I2C /* I2C with hardware support */
337 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
338 #define CONFIG_I2C_MULTI_BUS
339 #define CONFIG_I2C_CMD_TREE
340 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
341 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
342 #define CONFIG_SYS_I2C_SLAVE 0x7F
343 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
344 #define CONFIG_SYS_I2C_OFFSET 0x3000
345 #define CONFIG_SYS_I2C2_OFFSET 0x3100
350 #define CONFIG_ID_EEPROM
351 #ifdef CONFIG_ID_EEPROM
352 #define CONFIG_SYS_I2C_EEPROM_NXID
354 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
355 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
356 #define CONFIG_SYS_EEPROM_BUS_NUM 1
358 #define CONFIG_RTC_DS1337
359 #define CONFIG_SYS_RTC_DS1337_NOOSC
360 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
363 * Memory space is mapped 1-1, but I/O space must start from 0.
366 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
367 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
368 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
369 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
370 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
371 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
372 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
373 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
374 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
375 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
377 /* controller 1, Slot 1, tgtid 1, Base address a000 */
378 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
379 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
380 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
381 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
382 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
383 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
384 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
385 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
388 #if defined(CONFIG_PCI)
389 #define CONFIG_NET_MULTI
390 #define CONFIG_PCI_PNP /* do pci plug-and-play */
392 #undef CONFIG_EEPRO100
394 #undef CONFIG_RTL8139
396 #ifdef CONFIG_RTL8139
397 /* This macro is used by RTL8139 but not defined in PPC architecture */
398 #define KSEG1ADDR(x) (x)
399 #define _IO_BASE 0x00000000
403 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
404 #define CONFIG_DOS_PARTITION
406 #endif /* CONFIG_PCI */
408 #if defined(CONFIG_TSEC_ENET)
409 #ifndef CONFIG_NET_MULTI
410 #define CONFIG_NET_MULTI 1
413 #define CONFIG_MII 1 /* MII PHY management */
414 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
415 #define CONFIG_TSEC1 1
416 #define CONFIG_TSEC1_NAME "eTSEC1"
417 #define CONFIG_TSEC2 1
418 #define CONFIG_TSEC2_NAME "eTSEC2"
419 #define CONFIG_TSEC3 1
420 #define CONFIG_TSEC3_NAME "eTSEC3"
422 #define TSEC1_PHY_ADDR 2
423 #define TSEC2_PHY_ADDR 0
424 #define TSEC3_PHY_ADDR 1
426 #define CONFIG_VSC7385_ENET
428 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
429 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
430 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432 #define TSEC1_PHYIDX 0
433 #define TSEC2_PHYIDX 0
434 #define TSEC3_PHYIDX 0
438 #ifdef CONFIG_VSC7385_ENET
439 /* The size of the VSC7385 firmware image */
440 #define CONFIG_VSC7385_IMAGE_SIZE 8192
443 #define CONFIG_ETHPRIME "eTSEC1"
445 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
447 #endif /* CONFIG_TSEC_ENET */
452 #if defined(CONFIG_SYS_RAMBOOT)
453 #if defined(CONFIG_RAMBOOT_NAND)
454 #define CONFIG_ENV_IS_IN_NAND 1
455 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
456 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
457 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
458 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
459 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
460 #define CONFIG_ENV_SIZE 0x2000
463 #define CONFIG_ENV_IS_IN_FLASH 1
464 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
465 #define CONFIG_ENV_ADDR 0xfff80000
467 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
469 #define CONFIG_ENV_SIZE 0x2000
470 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
473 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
474 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
477 * Command line configuration.
479 #include <config_cmd_default.h>
481 #define CONFIG_CMD_DATE
482 #define CONFIG_CMD_ELF
483 #define CONFIG_CMD_I2C
484 #define CONFIG_CMD_IRQ
485 #define CONFIG_CMD_MII
486 #define CONFIG_CMD_PING
487 #define CONFIG_CMD_SETEXPR
488 #define CONFIG_CMD_REGINFO
490 #if defined(CONFIG_PCI)
491 #define CONFIG_CMD_NET
492 #define CONFIG_CMD_PCI
495 #undef CONFIG_WATCHDOG /* watchdog disabled */
500 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
501 #define CONFIG_CMD_MMC
502 #define CONFIG_DOS_PARTITION
503 #define CONFIG_FSL_ESDHC
504 #define CONFIG_GENERIC_MMC
505 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
507 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
511 #define CONFIG_USB_EHCI
513 #ifdef CONFIG_USB_EHCI
514 #define CONFIG_CMD_USB
515 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
516 #define CONFIG_USB_EHCI_FSL
517 #define CONFIG_USB_STORAGE
520 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
521 #define CONFIG_CMD_EXT2
522 #define CONFIG_CMD_FAT
523 #define CONFIG_DOS_PARTITION
527 * Miscellaneous configurable options
529 #define CONFIG_SYS_LONGHELP /* undef to save memory */
530 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
531 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
532 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
533 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
534 #if defined(CONFIG_CMD_KGDB)
535 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
537 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
539 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
540 /* Print Buffer Size */
541 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
542 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
543 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
546 * For booting Linux, the board info and command line data
547 * have to be in the first 16 MB of memory, since this is
548 * the maximum mapped by the Linux kernel during initialization.
550 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
551 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
553 #if defined(CONFIG_CMD_KGDB)
554 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
555 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
559 * Environment Configuration
562 #if defined(CONFIG_TSEC_ENET)
563 #define CONFIG_HAS_ETH0
564 #define CONFIG_HAS_ETH1
565 #define CONFIG_HAS_ETH2
568 #define CONFIG_HOSTNAME P2020RDB
569 #define CONFIG_ROOTPATH /opt/nfsroot
570 #define CONFIG_BOOTFILE uImage
571 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
573 /* default location for tftp and bootm */
574 #define CONFIG_LOADADDR 1000000
576 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
577 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
579 #define CONFIG_BAUDRATE 115200
581 #define CONFIG_EXTRA_ENV_SETTINGS \
583 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
584 "loadaddr=1000000\0" \
585 "tftpflash=tftpboot $loadaddr $uboot; " \
586 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
587 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
588 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
589 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
590 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
591 "consoledev=ttyS0\0" \
592 "ramdiskaddr=2000000\0" \
593 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
595 "fdtfile=p2020rdb.dtb\0" \
597 "jffs2nor=mtdblock3\0" \
598 "norbootaddr=ef080000\0" \
599 "norfdtaddr=ef040000\0" \
600 "jffs2nand=mtdblock9\0" \
601 "nandbootaddr=100000\0" \
602 "nandfdtaddr=80000\0" \
603 "nandimgsize=400000\0" \
604 "nandfdtsize=80000\0" \
605 "usb_phy_type=ulpi\0" \
606 "vscfw_addr=ef000000\0" \
607 "othbootargs=ramdisk_size=600000\0" \
608 "usbfatboot=setenv bootargs root=/dev/ram rw " \
609 "console=$consoledev,$baudrate $othbootargs; " \
611 "fatload usb 0:2 $loadaddr $bootfile;" \
612 "fatload usb 0:2 $fdtaddr $fdtfile;" \
613 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
615 "usbext2boot=setenv bootargs root=/dev/ram rw " \
616 "console=$consoledev,$baudrate $othbootargs; " \
618 "ext2load usb 0:4 $loadaddr $bootfile;" \
619 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
620 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
622 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
623 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
624 "bootm $norbootaddr - $norfdtaddr\0" \
625 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "nand read 2000000 $nandbootaddr $nandimgsize;" \
628 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
629 "bootm 2000000 - 3000000;\0"
631 #define CONFIG_NFSBOOTCOMMAND \
632 "setenv bootargs root=/dev/nfs rw " \
633 "nfsroot=$serverip:$rootpath " \
634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr - $fdtaddr"
640 #define CONFIG_HDBOOT \
641 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
642 "console=$consoledev,$baudrate $othbootargs;" \
644 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
645 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
646 "bootm $loadaddr - $fdtaddr"
648 #define CONFIG_RAMBOOTCOMMAND \
649 "setenv bootargs root=/dev/ram rw " \
650 "console=$consoledev,$baudrate $othbootargs; " \
651 "tftp $ramdiskaddr $ramdiskfile;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr $ramdiskaddr $fdtaddr"
656 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
658 #endif /* __CONFIG_H */