2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
33 /* High Level Configuration Options */
34 #define CONFIG_BOOKE 1 /* BOOKE */
35 #define CONFIG_E500 1 /* BOOKE e500 family */
36 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
37 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
38 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
39 #define CONFIG_TSEC_ENET /* tsec ethernet support */
40 #define CONFIG_ENV_OVERWRITE
43 extern unsigned long get_board_sys_clk(unsigned long dummy);
45 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
48 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
53 * These can be toggled for performance analysis, otherwise use default.
55 #define CONFIG_L2_CACHE /* toggle L2 cache */
56 #define CONFIG_BTB /* toggle branch predition */
58 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
60 #define CONFIG_ENABLE_36BIT_PHYS 1
62 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
64 #define CONFIG_PANIC_HANG /* do not reset board on panic */
67 * Base addresses -- Note these are effective addresses where the
68 * actual resources get mapped (not physical addresses)
70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
71 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
72 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
74 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
76 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
77 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
80 #define CONFIG_FSL_DDR2
81 #undef CONFIG_FSL_DDR_INTERACTIVE
82 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
87 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
91 #define CONFIG_NUM_DDR_CONTROLLERS 1
92 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
93 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
95 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
96 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
97 #define CONFIG_SYS_DDR_SBE 0x00FF0000
99 #define CONFIG_SYS_DDR_TLB_START 9
104 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
105 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
106 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
108 * Localbus cacheable (TBD)
109 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
111 * Localbus non-cacheable
112 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
113 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
114 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
115 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
116 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
120 * Local Bus Definitions
122 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
124 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
126 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
128 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
130 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
131 #define CONFIG_SYS_FLASH_QUIET_TEST
132 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
135 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
136 #undef CONFIG_SYS_FLASH_CHECKSUM
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
140 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
142 #define CONFIG_FLASH_CFI_DRIVER
143 #define CONFIG_SYS_FLASH_CFI
144 #define CONFIG_SYS_FLASH_EMPTY_INFO
145 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
147 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
149 #define CONFIG_SYS_INIT_RAM_LOCK 1
150 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
151 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
153 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
154 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
155 - CONFIG_SYS_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
158 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
159 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
161 #define CONFIG_SYS_NAND_BASE 0xffa00000
162 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
163 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
164 #define CONFIG_SYS_MAX_NAND_DEVICE 1
165 #define NAND_MAX_CHIPS 1
166 #define CONFIG_MTD_NAND_VERIFY_WRITE
167 #define CONFIG_CMD_NAND 1
168 #define CONFIG_NAND_FSL_ELBC 1
169 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
171 /* NAND flash config */
172 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
173 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
174 | BR_PS_8 /* Port Size = 8 bit */ \
175 | BR_MS_FCM /* MSEL = FCM */ \
178 #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
186 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
187 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
188 #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
189 #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
191 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
193 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
195 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
196 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
197 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
198 OR_GPCM_EHTR | OR_GPCM_EAD)
200 /* Serial Port - controlled on board with jumper J8
204 #define CONFIG_CONS_INDEX 1
205 //#define CONFIG_CONS_INDEX 2
206 #undef CONFIG_SERIAL_SOFTWARE_FIFO
207 #define CONFIG_SYS_NS16550
208 #define CONFIG_SYS_NS16550_SERIAL
209 #define CONFIG_SYS_NS16550_REG_SIZE 1
210 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
212 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
213 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
215 #define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
218 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
219 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
221 /* Use the HUSH parser */
222 #define CONFIG_SYS_HUSH_PARSER
223 #ifdef CONFIG_SYS_HUSH_PARSER
224 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
228 * Pass open firmware flat tree
230 #define CONFIG_OF_LIBFDT 1
231 #define CONFIG_OF_BOARD_SETUP 1
232 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
234 #define CONFIG_SYS_64BIT_VSPRINTF 1
235 #define CONFIG_SYS_64BIT_STRTOUL 1
237 /* new uImage format support */
239 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
242 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
243 #define CONFIG_HARD_I2C /* I2C with hardware support */
244 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
245 #define CONFIG_I2C_MULTI_BUS
246 #define CONFIG_I2C_CMD_TREE
247 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
249 #define CONFIG_SYS_I2C_SLAVE 0x7F
250 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
251 #define CONFIG_SYS_I2C_OFFSET 0x3000
252 #define CONFIG_SYS_I2C2_OFFSET 0x3100
257 #define CONFIG_ID_EEPROM
258 #ifdef CONFIG_ID_EEPROM
259 #define CONFIG_SYS_I2C_EEPROM_NXID
261 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
262 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
263 #define CONFIG_SYS_EEPROM_BUS_NUM 1
265 #define CONFIG_RTC_DS1337
266 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
269 * Memory space is mapped 1-1, but I/O space must start from 0.
272 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
273 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
274 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
275 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
276 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
277 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
278 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
279 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
280 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
282 /* controller 1, Slot 1, tgtid 1, Base address a000 */
283 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
284 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
285 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
286 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
287 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
288 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
289 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
290 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
292 #if defined(CONFIG_PCI)
293 #define CONFIG_NET_MULTI
294 #define CONFIG_PCI_PNP /* do pci plug-and-play */
296 #undef CONFIG_EEPRO100
298 #undef CONFIG_RTL8139
300 #ifdef CONFIG_RTL8139
301 /* This macro is used by RTL8139 but not defined in PPC architecture */
302 #define KSEG1ADDR(x) (x)
303 #define _IO_BASE 0x00000000
307 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
308 #define CONFIG_DOS_PARTITION
310 #endif /* CONFIG_PCI */
312 #if defined(CONFIG_TSEC_ENET)
313 #ifndef CONFIG_NET_MULTI
314 #define CONFIG_NET_MULTI 1
317 #define CONFIG_MII 1 /* MII PHY management */
318 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
319 #define CONFIG_TSEC1 1
320 #define CONFIG_TSEC1_NAME "eTSEC1"
321 #define CONFIG_TSEC2 1
322 #define CONFIG_TSEC2_NAME "eTSEC2"
323 #define CONFIG_TSEC3 1
324 #define CONFIG_TSEC3_NAME "eTSEC3"
326 #define TSEC1_PHY_ADDR 2
327 #define TSEC2_PHY_ADDR 0
328 #define TSEC3_PHY_ADDR 1
330 #define CONFIG_VSC7385_ENET
332 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
333 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
334 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336 #define TSEC1_PHYIDX 0
337 #define TSEC2_PHYIDX 0
338 #define TSEC3_PHYIDX 0
342 #ifdef CONFIG_VSC7385_ENET
343 /* The size of the VSC7385 firmware image */
344 #define CONFIG_VSC7385_IMAGE_SIZE 8192
347 #define CONFIG_ETHPRIME "eTSEC1"
349 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
350 #endif /* CONFIG_TSEC_ENET */
355 #define CONFIG_ENV_IS_IN_FLASH 1
356 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
357 #define CONFIG_ENV_ADDR 0xfff80000
359 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
361 #define CONFIG_ENV_SIZE 0x2000
362 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
364 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
365 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
368 * Command line configuration.
370 #include <config_cmd_default.h>
372 #define CONFIG_CMD_DATE
373 #define CONFIG_CMD_ELF
374 #define CONFIG_CMD_I2C
375 #define CONFIG_CMD_IRQ
376 #define CONFIG_CMD_MII
377 #define CONFIG_CMD_PING
378 #define CONFIG_CMD_SETEXPR
380 #if defined(CONFIG_PCI)
381 #define CONFIG_CMD_BEDBUG
382 #define CONFIG_CMD_NET
383 #define CONFIG_CMD_PCI
386 #undef CONFIG_WATCHDOG /* watchdog disabled */
391 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
392 #define CONFIG_CMD_MMC
393 #define CONFIG_DOS_PARTITION
394 #define CONFIG_FSL_ESDHC
395 #define CONFIG_GENERIC_MMC
396 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
398 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
402 #define CONFIG_USB_EHCI
404 #ifdef CONFIG_USB_EHCI
405 #define CONFIG_CMD_USB
406 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
407 #define CONFIG_USB_EHCI_FSL
408 #define CONFIG_USB_STORAGE
411 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
412 #define CONFIG_CMD_EXT2
413 #define CONFIG_CMD_FAT
414 #define CONFIG_DOS_PARTITION
418 * Miscellaneous configurable options
420 #define CONFIG_SYS_LONGHELP /* undef to save memory */
421 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
422 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
423 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
424 #if defined(CONFIG_CMD_KGDB)
425 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
427 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
429 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
430 /* Print Buffer Size */
431 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
432 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
433 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
436 * For booting Linux, the board info and command line data
437 * have to be in the first 16 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
440 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
443 * Internal Definitions
447 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
448 #define BOOTFLAG_WARM 0x02 /* Software reboot */
450 #if defined(CONFIG_CMD_KGDB)
451 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
452 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
456 * Environment Configuration
459 #if defined(CONFIG_TSEC_ENET)
460 #define CONFIG_HAS_ETH0
461 #define CONFIG_HAS_ETH1
462 #define CONFIG_HAS_ETH2
465 #define CONFIG_HOSTNAME P2020RDB
466 #define CONFIG_ROOTPATH /opt/nfsroot
467 #define CONFIG_BOOTFILE uImage
468 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
470 /* default location for tftp and bootm */
471 #define CONFIG_LOADADDR 1000000
473 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
474 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
476 #define CONFIG_BAUDRATE 115200
478 #define CONFIG_EXTRA_ENV_SETTINGS \
480 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
481 "loadaddr=1000000\0" \
482 "bootfile=uImage\0" \
483 "tftpflash=tftpboot $loadaddr $uboot; " \
484 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
485 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
486 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
487 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
488 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
489 "consoledev=ttyS0\0" \
490 "ramdiskaddr=2000000\0" \
491 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
493 "fdtfile=p2020rdb.dtb\0" \
495 "jffs2nor=mtdblock3\0" \
496 "norbootaddr=ef080000\0" \
497 "norfdtaddr=ef040000\0" \
498 "jffs2nand=mtdblock9\0" \
499 "nandbootaddr=100000\0" \
500 "nandfdtaddr=80000\0" \
501 "nandimgsize=400000\0" \
502 "nandfdtsize=80000\0" \
503 "usb_phy_type=ulpi\0" \
504 "vscfw_addr=ef000000\0" \
505 "othbootargs=ramdisk_size=600000\0" \
506 "usbfatboot=setenv bootargs root=/dev/ram rw " \
507 "console=$consoledev,$baudrate $othbootargs; " \
509 "fatload usb 0:2 $loadaddr $bootfile;" \
510 "fatload usb 0:2 $fdtaddr $fdtfile;" \
511 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
512 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
513 "usbext2boot=setenv bootargs root=/dev/ram rw " \
514 "console=$consoledev,$baudrate $othbootargs; " \
516 "ext2load usb 0:4 $loadaddr $bootfile;" \
517 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
518 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
519 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
520 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
521 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
522 "bootm $norbootaddr - $norfdtaddr\0" \
523 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
524 "console=$consoledev,$baudrate $othbootargs;" \
525 "nand read 2000000 $nandbootaddr $nandimgsize;" \
526 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
527 "bootm 2000000 - 3000000;\0"
529 #define CONFIG_NFSBOOTCOMMAND \
530 "setenv bootargs root=/dev/nfs rw " \
531 "nfsroot=$serverip:$rootpath " \
532 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
533 "console=$consoledev,$baudrate $othbootargs;" \
534 "tftp $loadaddr $bootfile;" \
535 "tftp $fdtaddr $fdtfile;" \
536 "bootm $loadaddr - $fdtaddr"
538 #define CONFIG_HDBOOT \
539 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
540 "console=$consoledev,$baudrate $othbootargs;" \
542 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
543 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
544 "bootm $loadaddr - $fdtaddr"
546 #define CONFIG_RAMBOOTCOMMAND \
547 "setenv bootargs root=/dev/ram rw " \
548 "console=$consoledev,$baudrate $othbootargs; " \
549 "tftp $ramdiskaddr $ramdiskfile;" \
550 "tftp $loadaddr $bootfile;" \
551 "tftp $fdtaddr $fdtfile;" \
552 "bootm $loadaddr $ramdiskaddr $fdtaddr"
554 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
556 #endif /* __CONFIG_H */