2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 #ifdef CONFIG_MK_36BIT
31 #define CONFIG_PHYS_64BIT
34 /* High Level Configuration Options */
35 #define CONFIG_BOOKE 1 /* BOOKE */
36 #define CONFIG_E500 1 /* BOOKE e500 family */
37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38 #define CONFIG_P2020 1
39 #define CONFIG_P2020DS 1
40 #define CONFIG_MP 1 /* support multiple processors */
42 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
43 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
54 #define CONFIG_TSEC_ENET /* tsec ethernet support */
55 #define CONFIG_ENV_OVERWRITE
58 extern unsigned long calculate_board_sys_clk(unsigned long dummy);
59 extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
60 /* extern unsigned long get_board_sys_clk(unsigned long dummy); */
61 /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
63 #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
67 from ICS307 instead of switches */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ENABLE_36BIT_PHYS 1
77 #ifdef CONFIG_PHYS_64BIT
78 #define CONFIG_ADDR_MAP 1
79 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
82 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
83 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
84 #define CONFIG_PANIC_HANG /* do not reset board on panic */
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
92 #ifdef CONFIG_PHYS_64BIT
93 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
99 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
100 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
101 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
104 #define CONFIG_SYS_DDR_TLB_START 9
105 #define CONFIG_VERY_BIG_RAM
106 #define CONFIG_FSL_DDR3 1
107 #undef CONFIG_FSL_DDR_INTERACTIVE
109 /* ECC will be enabled based on perf_mode environment variable */
110 /* #define CONFIG_DDR_ECC */
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
118 #define CONFIG_NUM_DDR_CONTROLLERS 1
119 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
120 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
122 /* I2C addresses of SPD EEPROMs */
123 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
124 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
126 /* These are used when DDR doesn't use SPD. */
127 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
129 /* Default settings for "stable" mode */
130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
131 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
132 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
133 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
134 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
135 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
136 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
137 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
138 #define CONFIG_SYS_DDR_MODE_1 0x00421422
139 #define CONFIG_SYS_DDR_MODE_2 0x00000000
140 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
141 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
142 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
143 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
144 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
145 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
146 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
147 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
148 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
149 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
150 #define CONFIG_SYS_DDR_CDR1 0x00040000
151 #define CONFIG_SYS_DDR_CDR2 0x00000000
153 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
154 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
155 #define CONFIG_SYS_DDR_SBE 0x00010000
157 /* Settings that differ for "performance" mode */
158 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
159 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
160 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
161 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
162 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
163 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
166 * The following set of values were tested for DDR2
167 * with a DDR3 to DDR2 interposer
169 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
170 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
171 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
172 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
173 #define CONFIG_SYS_DDR_MODE_1 0x00480432
174 #define CONFIG_SYS_DDR_MODE_2 0x00000000
175 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
176 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
177 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
178 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
179 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
180 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
181 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
185 #undef CONFIG_CLOCKS_IN_MHZ
190 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
191 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
192 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
193 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
195 * Localbus cacheable (TBD)
196 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
198 * Localbus non-cacheable
199 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
200 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
201 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
202 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
203 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
204 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
208 * Local Bus Definitions
210 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
211 #ifdef CONFIG_PHYS_64BIT
212 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
214 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
217 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
218 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
220 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
221 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
223 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
224 #define CONFIG_SYS_FLASH_QUIET_TEST
225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
227 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
229 #undef CONFIG_SYS_FLASH_CHECKSUM
230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
233 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
235 #define CONFIG_FLASH_CFI_DRIVER
236 #define CONFIG_SYS_FLASH_CFI
237 #define CONFIG_SYS_FLASH_EMPTY_INFO
238 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
240 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
242 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
243 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
244 #ifdef CONFIG_PHYS_64BIT
245 #define PIXIS_BASE_PHYS 0xfffdf0000ull
247 #define PIXIS_BASE_PHYS PIXIS_BASE
250 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
251 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
253 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
254 #define PIXIS_VER 0x1 /* Board version at offset 1 */
255 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
256 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
257 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
258 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
259 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
260 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
261 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
262 #define PIXIS_VCTL 0x10 /* VELA Control Register */
263 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
264 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
265 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
266 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
267 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
268 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
269 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
270 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
271 #define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
272 #define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
273 #define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
274 #define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
275 #define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
276 #define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
278 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
279 #define PIXIS_LED 0x25 /* LED Register */
281 #define PIXIS_SW(x) 0x20 + (x - 1) * 2
282 #define PIXIS_EN(x) 0x21 + (x - 1) * 2
283 #define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
284 #define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
286 /* old pixis referenced names */
287 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
288 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
289 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
290 #define PIXIS_VSPEED2_TSEC1SER 0x8
291 #define PIXIS_VSPEED2_TSEC2SER 0x4
292 #define PIXIS_VSPEED2_TSEC3SER 0x2
293 #define PIXIS_VSPEED2_TSEC4SER 0x1
294 #define PIXIS_VCFGEN1_TSEC1SER 0x20
295 #define PIXIS_VCFGEN1_TSEC2SER 0x20
296 #define PIXIS_VCFGEN1_TSEC3SER 0x20
297 #define PIXIS_VCFGEN1_TSEC4SER 0x20
298 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
299 | PIXIS_VSPEED2_TSEC2SER \
300 | PIXIS_VSPEED2_TSEC3SER \
301 | PIXIS_VSPEED2_TSEC4SER)
302 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
303 | PIXIS_VCFGEN1_TSEC2SER \
304 | PIXIS_VCFGEN1_TSEC3SER \
305 | PIXIS_VCFGEN1_TSEC4SER)
307 #define CONFIG_SYS_INIT_RAM_LOCK 1
308 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
309 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
311 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
312 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
313 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
316 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
318 #define CONFIG_SYS_NAND_BASE 0xffa00000
319 #ifdef CONFIG_PHYS_64BIT
320 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
322 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
324 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
325 CONFIG_SYS_NAND_BASE + 0x40000, \
326 CONFIG_SYS_NAND_BASE + 0x80000,\
327 CONFIG_SYS_NAND_BASE + 0xC0000}
328 #define CONFIG_SYS_MAX_NAND_DEVICE 4
329 #define CONFIG_MTD_NAND_VERIFY_WRITE
330 #define CONFIG_CMD_NAND 1
331 #define CONFIG_NAND_FSL_ELBC 1
332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
334 /* NAND flash config */
335 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
336 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
337 | BR_PS_8 /* Port Size = 8bit */ \
338 | BR_MS_FCM /* MSEL = FCM */ \
340 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
341 | OR_FCM_PGS /* Large Page*/ \
349 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
350 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
351 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
352 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
354 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
355 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
356 | BR_PS_8 /* Port Size = 8bit */ \
357 | BR_MS_FCM /* MSEL = FCM */ \
359 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
360 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
361 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
362 | BR_PS_8 /* Port Size = 8bit */ \
363 | BR_MS_FCM /* MSEL = FCM */ \
365 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
367 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
368 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
369 | BR_PS_8 /* Port Size = 8bit */ \
370 | BR_MS_FCM /* MSEL = FCM */ \
372 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
374 /* Serial Port - controlled on board with jumper J8
378 #define CONFIG_CONS_INDEX 1
379 #undef CONFIG_SERIAL_SOFTWARE_FIFO
380 #define CONFIG_SYS_NS16550
381 #define CONFIG_SYS_NS16550_SERIAL
382 #define CONFIG_SYS_NS16550_REG_SIZE 1
383 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
385 #define CONFIG_SYS_BAUDRATE_TABLE \
386 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
388 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
389 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
391 /* Use the HUSH parser */
392 #define CONFIG_SYS_HUSH_PARSER
393 #ifdef CONFIG_SYS_HUSH_PARSER
394 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
398 * Pass open firmware flat tree
400 #define CONFIG_OF_LIBFDT 1
401 #define CONFIG_OF_BOARD_SETUP 1
402 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
404 #define CONFIG_SYS_64BIT_VSPRINTF 1
405 #define CONFIG_SYS_64BIT_STRTOUL 1
407 /* new uImage format support */
409 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
412 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
413 #define CONFIG_HARD_I2C /* I2C with hardware support */
414 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
415 #define CONFIG_I2C_MULTI_BUS
416 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
417 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
418 #define CONFIG_SYS_I2C_SLAVE 0x7F
419 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
420 #define CONFIG_SYS_I2C_OFFSET 0x3000
421 #define CONFIG_SYS_I2C2_OFFSET 0x3100
426 #define CONFIG_ID_EEPROM
427 #ifdef CONFIG_ID_EEPROM
428 #define CONFIG_SYS_I2C_EEPROM_NXID
430 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
431 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
432 #define CONFIG_SYS_EEPROM_BUS_NUM 0
436 * Memory space is mapped 1-1, but I/O space must start from 0.
439 /* controller 3, Slot 1, tgtid 3, Base address b000 */
440 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
441 #ifdef CONFIG_PHYS_64BIT
442 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
443 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
445 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
446 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
448 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
449 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
450 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
454 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
456 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
458 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
459 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
460 #ifdef CONFIG_PHYS_64BIT
461 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
464 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
465 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
467 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
468 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
469 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
473 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
475 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477 /* controller 1, Slot 2, tgtid 1, Base address a000 */
478 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
479 #ifdef CONFIG_PHYS_64BIT
480 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
483 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
486 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
487 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
488 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
489 #ifdef CONFIG_PHYS_64BIT
490 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
492 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
494 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
496 #if defined(CONFIG_PCI)
498 /*PCIE video card used*/
499 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
504 #if defined(CONFIG_VIDEO)
505 #define CONFIG_BIOSEMU
506 #define CONFIG_CFB_CONSOLE
507 #define CONFIG_VIDEO_SW_CURSOR
508 #define CONFIG_VGA_AS_SINGLE_DEVICE
509 #define CONFIG_ATI_RADEON_FB
510 #define CONFIG_VIDEO_LOGO
511 /*#define CONFIG_CONSOLE_CURSOR*/
512 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
515 #define CONFIG_NET_MULTI
516 #define CONFIG_PCI_PNP /* do pci plug-and-play */
518 #undef CONFIG_EEPRO100
520 #define CONFIG_RTL8139
522 #ifndef CONFIG_PCI_PNP
523 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
524 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
525 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
528 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
529 #define CONFIG_DOS_PARTITION
530 #define CONFIG_SCSI_AHCI
532 #ifdef CONFIG_SCSI_AHCI
533 #define CONFIG_SATA_ULI5288
534 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
535 #define CONFIG_SYS_SCSI_MAX_LUN 1
536 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
537 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
540 #endif /* CONFIG_PCI */
543 #if defined(CONFIG_TSEC_ENET)
545 #ifndef CONFIG_NET_MULTI
546 #define CONFIG_NET_MULTI 1
549 #define CONFIG_MII 1 /* MII PHY management */
550 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
551 #define CONFIG_TSEC1 1
552 #define CONFIG_TSEC1_NAME "eTSEC1"
553 #define CONFIG_TSEC2 1
554 #define CONFIG_TSEC2_NAME "eTSEC2"
555 #define CONFIG_TSEC3 1
556 #define CONFIG_TSEC3_NAME "eTSEC3"
558 #define CONFIG_PIXIS_SGMII_CMD
559 #define CONFIG_FSL_SGMII_RISER 1
560 #define SGMII_RISER_PHY_OFFSET 0x1b
562 #ifdef CONFIG_FSL_SGMII_RISER
563 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
566 #define TSEC1_PHY_ADDR 0
567 #define TSEC2_PHY_ADDR 1
568 #define TSEC3_PHY_ADDR 2
570 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
571 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
572 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
574 #define TSEC1_PHYIDX 0
575 #define TSEC2_PHYIDX 0
576 #define TSEC3_PHYIDX 0
578 #define CONFIG_ETHPRIME "eTSEC1"
580 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
581 #endif /* CONFIG_TSEC_ENET */
586 #define CONFIG_ENV_IS_IN_FLASH 1
587 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
588 #define CONFIG_ENV_ADDR 0xfff80000
590 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
592 #define CONFIG_ENV_SIZE 0x2000
593 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
595 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
596 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
599 * Command line configuration.
601 #include <config_cmd_default.h>
603 #define CONFIG_CMD_IRQ
604 #define CONFIG_CMD_PING
605 #define CONFIG_CMD_I2C
606 #define CONFIG_CMD_MII
607 #define CONFIG_CMD_ELF
608 #define CONFIG_CMD_IRQ
609 #define CONFIG_CMD_SETEXPR
611 #if defined(CONFIG_PCI)
612 #define CONFIG_CMD_PCI
613 #define CONFIG_CMD_NET
614 #define CONFIG_CMD_SCSI
615 #define CONFIG_CMD_EXT2
621 #define CONFIG_CMD_USB
622 #define CONFIG_USB_STORAGE
623 #define CONFIG_USB_EHCI
624 #define CONFIG_USB_EHCI_FSL
625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
627 #undef CONFIG_WATCHDOG /* watchdog disabled */
630 * Miscellaneous configurable options
632 #define CONFIG_SYS_LONGHELP /* undef to save memory */
633 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
634 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
635 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
636 #if defined(CONFIG_CMD_KGDB)
637 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
639 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
641 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
642 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
643 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
644 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
647 * For booting Linux, the board info and command line data
648 * have to be in the first 16 MB of memory, since this is
649 * the maximum mapped by the Linux kernel during initialization.
651 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
654 * Internal Definitions
658 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
659 #define BOOTFLAG_WARM 0x02 /* Software reboot */
661 #if defined(CONFIG_CMD_KGDB)
662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
663 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
667 * Environment Configuration
670 /* The mac addresses for all ethernet interface */
671 #if defined(CONFIG_TSEC_ENET)
672 #define CONFIG_HAS_ETH0
673 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
674 #define CONFIG_HAS_ETH1
675 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
676 #define CONFIG_HAS_ETH2
677 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
678 #define CONFIG_HAS_ETH3
679 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
682 #define CONFIG_IPADDR 192.168.1.254
684 #define CONFIG_HOSTNAME unknown
685 #define CONFIG_ROOTPATH /opt/nfsroot
686 #define CONFIG_BOOTFILE uImage
687 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
689 #define CONFIG_SERVERIP 192.168.1.1
690 #define CONFIG_GATEWAYIP 192.168.1.1
691 #define CONFIG_NETMASK 255.255.255.0
693 /* default location for tftp and bootm */
694 #define CONFIG_LOADADDR 1000000
696 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
697 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
699 #define CONFIG_BAUDRATE 115200
701 #define CONFIG_EXTRA_ENV_SETTINGS \
702 "perf_mode=stable\0" \
703 "memctl_intlv_ctl=2\0" \
705 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
706 "tftpflash=tftpboot $loadaddr $uboot; " \
707 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
708 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
709 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
710 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
711 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
712 "consoledev=ttyS0\0" \
713 "ramdiskaddr=2000000\0" \
714 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
716 "fdtfile=p2020ds/p2020ds.dtb\0" \
719 #define CONFIG_HDBOOT \
720 "setenv bootargs root=/dev/$bdev rw " \
721 "console=$consoledev,$baudrate $othbootargs;" \
722 "tftp $loadaddr $bootfile;" \
723 "tftp $fdtaddr $fdtfile;" \
724 "bootm $loadaddr - $fdtaddr"
726 #define CONFIG_NFSBOOTCOMMAND \
727 "setenv bootargs root=/dev/nfs rw " \
728 "nfsroot=$serverip:$rootpath " \
729 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
730 "console=$consoledev,$baudrate $othbootargs;" \
731 "tftp $loadaddr $bootfile;" \
732 "tftp $fdtaddr $fdtfile;" \
733 "bootm $loadaddr - $fdtaddr"
735 #define CONFIG_RAMBOOTCOMMAND \
736 "setenv bootargs root=/dev/ram rw " \
737 "console=$consoledev,$baudrate $othbootargs;" \
738 "tftp $ramdiskaddr $ramdiskfile;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr $ramdiskaddr $fdtaddr"
743 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
745 #endif /* __CONFIG_H */