2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
40 #define CONFIG_P2020 1
41 #define CONFIG_P2020DS 1
42 #define CONFIG_MP 1 /* support multiple processors */
44 #ifndef CONFIG_SYS_TEXT_BASE
45 #define CONFIG_SYS_TEXT_BASE 0xeff80000
48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #define CONFIG_SYS_SRIO
53 #define CONFIG_SRIO1 /* SRIO port 1 */
54 #define CONFIG_SRIO2 /* SRIO port 2 */
56 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
57 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
58 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
59 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
60 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
61 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
62 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
63 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
65 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
66 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
68 #define CONFIG_TSEC_ENET /* tsec ethernet support */
69 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
72 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
73 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
76 * These can be toggled for performance analysis, otherwise use default.
78 #define CONFIG_L2_CACHE /* toggle L2 cache */
79 #define CONFIG_BTB /* toggle branch predition */
81 #define CONFIG_ENABLE_36BIT_PHYS 1
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_ADDR_MAP 1
85 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
88 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END 0x00400000
91 #define CONFIG_PANIC_HANG /* do not reset board on panic */
94 * Base addresses -- Note these are effective addresses where the
95 * actual resources get mapped (not physical addresses)
97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
98 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
99 #ifdef CONFIG_PHYS_64BIT
100 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
102 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
104 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
107 #define CONFIG_VERY_BIG_RAM
109 #define CONFIG_FSL_DDR2
111 #define CONFIG_FSL_DDR3 1
113 #undef CONFIG_FSL_DDR_INTERACTIVE
115 /* ECC will be enabled based on perf_mode environment variable */
116 /* #define CONFIG_DDR_ECC */
118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
119 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
121 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
124 #define CONFIG_NUM_DDR_CONTROLLERS 1
125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
126 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
128 /* I2C addresses of SPD EEPROMs */
129 #define CONFIG_DDR_SPD
130 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
131 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
133 /* These are used when DDR doesn't use SPD. */
134 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
136 /* Default settings for "stable" mode */
137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
138 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
139 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
140 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
141 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
142 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
143 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
144 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
145 #define CONFIG_SYS_DDR_MODE_1 0x00421422
146 #define CONFIG_SYS_DDR_MODE_2 0x00000000
147 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
148 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
150 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
151 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
152 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
153 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
154 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
155 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
156 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
157 #define CONFIG_SYS_DDR_CDR1 0x00040000
158 #define CONFIG_SYS_DDR_CDR2 0x00000000
160 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
161 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
162 #define CONFIG_SYS_DDR_SBE 0x00010000
164 /* Settings that differ for "performance" mode */
165 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
166 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
167 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
168 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
169 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
170 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
173 * The following set of values were tested for DDR2
174 * with a DDR3 to DDR2 interposer
176 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
177 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
178 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
179 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
180 #define CONFIG_SYS_DDR_MODE_1 0x00480432
181 #define CONFIG_SYS_DDR_MODE_2 0x00000000
182 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
183 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
184 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
185 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
186 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
187 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
188 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
192 #undef CONFIG_CLOCKS_IN_MHZ
197 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
198 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
199 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
200 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
202 * Localbus cacheable (TBD)
203 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
205 * Localbus non-cacheable
206 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
207 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
208 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
209 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
210 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
211 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
215 * Local Bus Definitions
217 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
221 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
224 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
225 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
227 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
228 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
230 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
231 #define CONFIG_SYS_FLASH_QUIET_TEST
232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
234 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
235 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
236 #undef CONFIG_SYS_FLASH_CHECKSUM
237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
242 #define CONFIG_FLASH_CFI_DRIVER
243 #define CONFIG_SYS_FLASH_CFI
244 #define CONFIG_SYS_FLASH_EMPTY_INFO
245 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
247 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
249 #define CONFIG_HWCONFIG /* enable hwconfig */
250 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
252 #ifdef CONFIG_FSL_NGPIXIS
253 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
254 #ifdef CONFIG_PHYS_64BIT
255 #define PIXIS_BASE_PHYS 0xfffdf0000ull
257 #define PIXIS_BASE_PHYS PIXIS_BASE
260 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
261 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
263 #define PIXIS_LBMAP_SWITCH 7
264 #define PIXIS_LBMAP_MASK 0xf0
265 #define PIXIS_LBMAP_SHIFT 4
266 #define PIXIS_LBMAP_ALTBANK 0x20
269 #define CONFIG_SYS_INIT_RAM_LOCK 1
270 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
271 #ifdef CONFIG_PHYS_64BIT
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
274 /* The assembler doesn't like typecast */
275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
283 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
285 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
286 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
288 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
289 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
291 #define CONFIG_SYS_NAND_BASE 0xffa00000
292 #ifdef CONFIG_PHYS_64BIT
293 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
295 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
297 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
298 CONFIG_SYS_NAND_BASE + 0x40000, \
299 CONFIG_SYS_NAND_BASE + 0x80000,\
300 CONFIG_SYS_NAND_BASE + 0xC0000}
301 #define CONFIG_SYS_MAX_NAND_DEVICE 4
302 #define CONFIG_MTD_NAND_VERIFY_WRITE
303 #define CONFIG_CMD_NAND 1
304 #define CONFIG_NAND_FSL_ELBC 1
305 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
307 /* NAND flash config */
308 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
313 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
314 | OR_FCM_PGS /* Large Page*/ \
322 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
323 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
324 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
325 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
327 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
328 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
329 | BR_PS_8 /* Port Size = 8bit */ \
330 | BR_MS_FCM /* MSEL = FCM */ \
332 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
333 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
334 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
335 | BR_PS_8 /* Port Size = 8bit */ \
336 | BR_MS_FCM /* MSEL = FCM */ \
338 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
340 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
341 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
342 | BR_PS_8 /* Port Size = 8bit */ \
343 | BR_MS_FCM /* MSEL = FCM */ \
345 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
347 /* Serial Port - controlled on board with jumper J8
351 #define CONFIG_CONS_INDEX 1
352 #define CONFIG_SYS_NS16550
353 #define CONFIG_SYS_NS16550_SERIAL
354 #define CONFIG_SYS_NS16550_REG_SIZE 1
355 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
357 #define CONFIG_SYS_BAUDRATE_TABLE \
358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
363 /* Use the HUSH parser */
364 #define CONFIG_SYS_HUSH_PARSER
365 #ifdef CONFIG_SYS_HUSH_PARSER
366 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
370 * Pass open firmware flat tree
372 #define CONFIG_OF_LIBFDT 1
373 #define CONFIG_OF_BOARD_SETUP 1
374 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
377 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
378 #define CONFIG_HARD_I2C /* I2C with hardware support */
379 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
380 #define CONFIG_I2C_MULTI_BUS
381 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
382 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
383 #define CONFIG_SYS_I2C_SLAVE 0x7F
384 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
385 #define CONFIG_SYS_I2C_OFFSET 0x3000
386 #define CONFIG_SYS_I2C2_OFFSET 0x3100
391 #define CONFIG_ID_EEPROM
392 #ifdef CONFIG_ID_EEPROM
393 #define CONFIG_SYS_I2C_EEPROM_NXID
395 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
396 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
397 #define CONFIG_SYS_EEPROM_BUS_NUM 0
401 * Memory space is mapped 1-1, but I/O space must start from 0.
404 /* controller 3, Slot 1, tgtid 3, Base address b000 */
405 #define CONFIG_SYS_PCIE3_NAME "Slot 1"
406 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
407 #ifdef CONFIG_PHYS_64BIT
408 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
409 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
411 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
412 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
414 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
415 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
416 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
420 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
422 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
424 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
425 #define CONFIG_SYS_PCIE2_NAME "ULI"
426 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
431 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
432 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
434 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
435 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
436 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
442 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
444 /* controller 1, Slot 2, tgtid 1, Base address a000 */
445 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
446 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
449 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
451 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
452 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
454 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
455 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
456 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
460 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
462 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
464 #if defined(CONFIG_PCI)
466 /*PCIE video card used*/
467 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
472 #if defined(CONFIG_VIDEO)
473 #define CONFIG_BIOSEMU
474 #define CONFIG_CFB_CONSOLE
475 #define CONFIG_VIDEO_SW_CURSOR
476 #define CONFIG_VGA_AS_SINGLE_DEVICE
477 #define CONFIG_ATI_RADEON_FB
478 #define CONFIG_VIDEO_LOGO
479 /*#define CONFIG_CONSOLE_CURSOR*/
480 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
483 /* SRIO1 uses the same window as PCIE2 mem window */
484 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
488 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
490 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
492 /* SRIO2 uses the same window as PCIE1 mem window */
493 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
494 #ifdef CONFIG_PHYS_64BIT
495 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
497 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
499 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
501 #define CONFIG_NET_MULTI
502 #define CONFIG_PCI_PNP /* do pci plug-and-play */
504 #undef CONFIG_EEPRO100
506 #define CONFIG_RTL8139
508 #ifndef CONFIG_PCI_PNP
509 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
510 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
511 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
514 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
515 #define CONFIG_DOS_PARTITION
516 #define CONFIG_SCSI_AHCI
518 #ifdef CONFIG_SCSI_AHCI
519 #define CONFIG_SATA_ULI5288
520 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
521 #define CONFIG_SYS_SCSI_MAX_LUN 1
522 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
523 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
526 #endif /* CONFIG_PCI */
529 #if defined(CONFIG_TSEC_ENET)
531 #ifndef CONFIG_NET_MULTI
532 #define CONFIG_NET_MULTI 1
535 #define CONFIG_MII 1 /* MII PHY management */
536 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
537 #define CONFIG_TSEC1 1
538 #define CONFIG_TSEC1_NAME "eTSEC1"
539 #define CONFIG_TSEC2 1
540 #define CONFIG_TSEC2_NAME "eTSEC2"
541 #define CONFIG_TSEC3 1
542 #define CONFIG_TSEC3_NAME "eTSEC3"
544 #define CONFIG_PIXIS_SGMII_CMD
545 #define CONFIG_FSL_SGMII_RISER 1
546 #define SGMII_RISER_PHY_OFFSET 0x1b
548 #ifdef CONFIG_FSL_SGMII_RISER
549 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
552 #define TSEC1_PHY_ADDR 0
553 #define TSEC2_PHY_ADDR 1
554 #define TSEC3_PHY_ADDR 2
556 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
557 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
558 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
560 #define TSEC1_PHYIDX 0
561 #define TSEC2_PHYIDX 0
562 #define TSEC3_PHYIDX 0
564 #define CONFIG_ETHPRIME "eTSEC1"
566 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
567 #endif /* CONFIG_TSEC_ENET */
572 #define CONFIG_ENV_IS_IN_FLASH 1
573 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
574 #define CONFIG_ENV_ADDR 0xfff80000
576 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
578 #define CONFIG_ENV_SIZE 0x2000
579 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
581 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
582 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
585 * Command line configuration.
587 #include <config_cmd_default.h>
589 #define CONFIG_CMD_IRQ
590 #define CONFIG_CMD_PING
591 #define CONFIG_CMD_I2C
592 #define CONFIG_CMD_MII
593 #define CONFIG_CMD_ELF
594 #define CONFIG_CMD_IRQ
595 #define CONFIG_CMD_SETEXPR
596 #define CONFIG_CMD_REGINFO
598 #if defined(CONFIG_PCI)
599 #define CONFIG_CMD_PCI
600 #define CONFIG_CMD_NET
601 #define CONFIG_CMD_SCSI
602 #define CONFIG_CMD_EXT2
608 #define CONFIG_CMD_USB
609 #define CONFIG_USB_STORAGE
610 #define CONFIG_USB_EHCI
611 #define CONFIG_USB_EHCI_FSL
612 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
614 #undef CONFIG_WATCHDOG /* watchdog disabled */
617 * Miscellaneous configurable options
619 #define CONFIG_SYS_LONGHELP /* undef to save memory */
620 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
621 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
622 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
623 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
624 #if defined(CONFIG_CMD_KGDB)
625 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
627 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
629 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
630 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
631 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
632 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
635 * For booting Linux, the board info and command line data
636 * have to be in the first 16 MB of memory, since this is
637 * the maximum mapped by the Linux kernel during initialization.
639 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
640 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
642 #if defined(CONFIG_CMD_KGDB)
643 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
644 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
648 * Environment Configuration
651 /* The mac addresses for all ethernet interface */
652 #if defined(CONFIG_TSEC_ENET)
653 #define CONFIG_HAS_ETH0
654 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
655 #define CONFIG_HAS_ETH1
656 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
657 #define CONFIG_HAS_ETH2
658 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
659 #define CONFIG_HAS_ETH3
660 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
663 #define CONFIG_IPADDR 192.168.1.254
665 #define CONFIG_HOSTNAME unknown
666 #define CONFIG_ROOTPATH /opt/nfsroot
667 #define CONFIG_BOOTFILE uImage
668 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
670 #define CONFIG_SERVERIP 192.168.1.1
671 #define CONFIG_GATEWAYIP 192.168.1.1
672 #define CONFIG_NETMASK 255.255.255.0
674 /* default location for tftp and bootm */
675 #define CONFIG_LOADADDR 1000000
677 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
678 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
680 #define CONFIG_BAUDRATE 115200
682 #define CONFIG_EXTRA_ENV_SETTINGS \
683 "perf_mode=stable\0" \
684 "memctl_intlv_ctl=2\0" \
686 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
687 "tftpflash=tftpboot $loadaddr $uboot; " \
688 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
689 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
690 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
691 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
692 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
693 "consoledev=ttyS0\0" \
694 "ramdiskaddr=2000000\0" \
695 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
697 "fdtfile=p2020ds/p2020ds.dtb\0" \
700 #define CONFIG_HDBOOT \
701 "setenv bootargs root=/dev/$bdev rw " \
702 "console=$consoledev,$baudrate $othbootargs;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr - $fdtaddr"
707 #define CONFIG_NFSBOOTCOMMAND \
708 "setenv bootargs root=/dev/nfs rw " \
709 "nfsroot=$serverip:$rootpath " \
710 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
711 "console=$consoledev,$baudrate $othbootargs;" \
712 "tftp $loadaddr $bootfile;" \
713 "tftp $fdtaddr $fdtfile;" \
714 "bootm $loadaddr - $fdtaddr"
716 #define CONFIG_RAMBOOTCOMMAND \
717 "setenv bootargs root=/dev/ram rw " \
718 "console=$consoledev,$baudrate $othbootargs;" \
719 "tftp $ramdiskaddr $ramdiskfile;" \
720 "tftp $loadaddr $bootfile;" \
721 "tftp $fdtaddr $fdtfile;" \
722 "bootm $loadaddr $ramdiskaddr $fdtaddr"
724 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
726 #endif /* __CONFIG_H */