2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #define CONFIG_P2041RDB
15 #define CONFIG_PHYS_64BIT
16 #define CONFIG_PPC_P2041
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
22 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
25 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
26 /* Set 1M boot space */
27 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
28 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
29 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #define CONFIG_SYS_NO_FLASH
34 /* High Level Configuration Options */
36 #define CONFIG_E500 /* BOOKE e500 family */
37 #define CONFIG_E500MC /* BOOKE e500mc family */
38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
40 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
41 #define CONFIG_MP /* support multiple processors */
43 #ifndef CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_TEXT_BASE 0xeff80000
47 #ifndef CONFIG_RESET_VECTOR_ADDRESS
48 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
52 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
53 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
54 #define CONFIG_PCI /* Enable PCI/PCIE */
55 #define CONFIG_PCIE1 /* PCIE controler 1 */
56 #define CONFIG_PCIE2 /* PCIE controler 2 */
57 #define CONFIG_PCIE3 /* PCIE controler 3 */
58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
59 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
61 #define CONFIG_SYS_SRIO
62 #define CONFIG_SRIO1 /* SRIO port 1 */
63 #define CONFIG_SRIO2 /* SRIO port 2 */
64 #define CONFIG_SRIO_PCIE_BOOT_MASTER
65 #define CONFIG_SYS_DPAA_RMAN /* RMan */
67 #define CONFIG_FSL_LAW /* Use common FSL init code */
69 #define CONFIG_ENV_OVERWRITE
71 #ifdef CONFIG_SYS_NO_FLASH
72 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
73 #define CONFIG_ENV_IS_NOWHERE
76 #define CONFIG_FLASH_CFI_DRIVER
77 #define CONFIG_SYS_FLASH_CFI
78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
81 #if defined(CONFIG_SPIFLASH)
82 #define CONFIG_SYS_EXTRA_ENV_RELOC
83 #define CONFIG_ENV_IS_IN_SPI_FLASH
84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE 0x10000
91 #elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_MMC
94 #define CONFIG_FSL_FIXED_MMC_LOCATION
95 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (512 * 1097)
98 #elif defined(CONFIG_NAND)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_NAND
101 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
102 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
104 #define CONFIG_ENV_IS_IN_REMOTE
105 #define CONFIG_ENV_ADDR 0xffe20000
106 #define CONFIG_ENV_SIZE 0x2000
107 #elif defined(CONFIG_ENV_IS_NOWHERE)
108 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
112 - CONFIG_ENV_SECT_SIZE)
113 #define CONFIG_ENV_SIZE 0x2000
114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
118 unsigned long get_board_sys_clk(unsigned long dummy);
120 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
123 * These can be toggled for performance analysis, otherwise use default.
125 #define CONFIG_SYS_CACHE_STASHING
126 #define CONFIG_BACKSIDE_L2_CACHE
127 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
128 #define CONFIG_BTB /* toggle branch predition */
130 #define CONFIG_ENABLE_36BIT_PHYS
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_ADDR_MAP
134 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x00400000
140 #define CONFIG_SYS_ALT_MEMTEST
141 #define CONFIG_PANIC_HANG /* do not reset board on panic */
144 * Config the L3 Cache as L3 SRAM
146 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
149 CONFIG_RAMBOOT_TEXT_BASE)
151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
153 #define CONFIG_SYS_L3_SIZE (1024 << 10)
154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
156 #ifdef CONFIG_PHYS_64BIT
157 #define CONFIG_SYS_DCSRBAR 0xf0000000
158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
162 #define CONFIG_ID_EEPROM
163 #define CONFIG_SYS_I2C_EEPROM_NXID
164 #define CONFIG_SYS_EEPROM_BUS_NUM 0
165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
171 #define CONFIG_VERY_BIG_RAM
172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
175 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
176 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
178 #define CONFIG_DDR_SPD
179 #define CONFIG_FSL_DDR3
181 #define CONFIG_SYS_SPD_BUS_NUM 0
182 #define SPD_EEPROM_ADDRESS 0x52
183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
186 * Local Bus Definitions
189 /* Set the local bus clock 1/8 of platform clock */
190 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
193 * This board doesn't have a promjet connector.
194 * However, it uses commone corenet board LAW and TLB.
195 * It is necessary to use the same start address with proper offset.
197 #define CONFIG_SYS_FLASH_BASE 0xe0000000
198 #ifdef CONFIG_PHYS_64BIT
199 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_FLASH_BR_PRELIM \
205 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
207 #define CONFIG_SYS_FLASH_OR_PRELIM \
208 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
209 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
211 #define CONFIG_FSL_CPLD
212 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
213 #ifdef CONFIG_PHYS_64BIT
214 #define CPLD_BASE_PHYS 0xfffdf0000ull
216 #define CPLD_BASE_PHYS CPLD_BASE
219 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
220 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
222 #define PIXIS_LBMAP_SWITCH 7
223 #define PIXIS_LBMAP_MASK 0xf0
224 #define PIXIS_LBMAP_SHIFT 4
225 #define PIXIS_LBMAP_ALTBANK 0x40
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
237 #if defined(CONFIG_RAMBOOT_PBL)
238 #define CONFIG_SYS_RAMBOOT
241 #define CONFIG_NAND_FSL_ELBC
243 #ifdef CONFIG_NAND_FSL_ELBC
244 #define CONFIG_SYS_NAND_BASE 0xffa00000
245 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
248 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
251 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
252 #define CONFIG_SYS_MAX_NAND_DEVICE 1
253 #define CONFIG_MTD_NAND_VERIFY_WRITE
254 #define CONFIG_CMD_NAND
255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
257 /* NAND flash config */
258 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
260 | BR_PS_8 /* Port Size = 8 bit */ \
261 | BR_MS_FCM /* MSEL = FCM */ \
263 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
264 | OR_FCM_PGS /* Large Page*/ \
273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
286 #endif /* CONFIG_NAND_FSL_ELBC */
288 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
290 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
292 #define CONFIG_BOARD_EARLY_INIT_F
293 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
294 #define CONFIG_MISC_INIT_R
296 #define CONFIG_HWCONFIG
298 /* define to use L1 as initial stack */
299 #define CONFIG_L1_INIT_RAM
300 #define CONFIG_SYS_INIT_RAM_LOCK
301 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
302 #ifdef CONFIG_PHYS_64BIT
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
305 /* The assembler doesn't like typecast */
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
307 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
308 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
320 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
321 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
323 /* Serial Port - controlled on board with jumper J8
327 #define CONFIG_CONS_INDEX 1
328 #define CONFIG_SYS_NS16550
329 #define CONFIG_SYS_NS16550_SERIAL
330 #define CONFIG_SYS_NS16550_REG_SIZE 1
331 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
333 #define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
341 /* Use the HUSH parser */
342 #define CONFIG_SYS_HUSH_PARSER
344 /* pass open firmware flat tree */
345 #define CONFIG_OF_LIBFDT
346 #define CONFIG_OF_BOARD_SETUP
347 #define CONFIG_OF_STDOUT_VIA_ALIAS
349 /* new uImage format support */
351 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
354 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
355 #define CONFIG_HARD_I2C /* I2C with hardware support */
356 #define CONFIG_I2C_MULTI_BUS
357 #define CONFIG_I2C_CMD_TREE
358 #define CONFIG_SYS_I2C_SPEED 400000
359 #define CONFIG_SYS_I2C_SLAVE 0x7F
360 #define CONFIG_SYS_I2C_OFFSET 0x118000
361 #define CONFIG_SYS_I2C2_OFFSET 0x118100
366 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
367 #ifdef CONFIG_PHYS_64BIT
368 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
370 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
372 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
374 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
375 #ifdef CONFIG_PHYS_64BIT
376 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
378 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
380 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
383 * for slave u-boot IMAGE instored in master memory space,
384 * PHYS must be aligned based on the SIZE
386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
391 * for slave UCODE and ENV instored in master memory space,
392 * PHYS must be aligned based on the SIZE
394 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
398 /* slave core release by master*/
399 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
400 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
403 * SRIO_PCIE_BOOT - SLAVE
405 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
406 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
407 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
408 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
412 * eSPI - Enhanced SPI
414 #define CONFIG_FSL_ESPI
415 #define CONFIG_SPI_FLASH
416 #define CONFIG_SPI_FLASH_SPANSION
417 #define CONFIG_CMD_SF
418 #define CONFIG_SF_DEFAULT_SPEED 10000000
419 #define CONFIG_SF_DEFAULT_MODE 0
423 * Memory space is mapped 1-1, but I/O space must start from 0.
426 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
427 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
430 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
432 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
433 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
435 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
436 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
437 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
441 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
443 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
445 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
446 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
449 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
451 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
452 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
454 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
455 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
456 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
462 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
464 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
465 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
466 #ifdef CONFIG_PHYS_64BIT
467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
470 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
471 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
473 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
474 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
475 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
481 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
484 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
485 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
486 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
487 #ifdef CONFIG_PHYS_64BIT
488 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
490 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
492 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
493 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
494 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
495 #ifdef CONFIG_PHYS_64BIT
496 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
498 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
500 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
502 #define CONFIG_SYS_DPAA_FMAN
503 #define CONFIG_SYS_DPAA_PME
504 /* Default address of microcode for the Linux Fman driver */
505 #if defined(CONFIG_SPIFLASH)
507 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
508 * env, so we got 0x110000.
510 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
511 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
512 #elif defined(CONFIG_SDCARD)
514 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
515 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
516 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
518 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
519 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
520 #elif defined(CONFIG_NAND)
521 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
522 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
523 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
525 * Slave has no ucode locally, it can fetch this from remote. When implementing
526 * in two corenet boards, slave's ucode could be stored in master's memory
527 * space, the address can be mapped from slave TLB->slave LAW->
528 * slave SRIO or PCIE outbound window->master inbound window->
529 * master LAW->the ucode address in master's memory space.
531 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
532 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
534 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
535 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
537 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
538 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
540 #ifdef CONFIG_SYS_DPAA_FMAN
541 #define CONFIG_FMAN_ENET
542 #define CONFIG_PHYLIB_10G
543 #define CONFIG_PHY_VITESSE
544 #define CONFIG_PHY_TERANETICS
548 #define CONFIG_PCI_INDIRECT_BRIDGE
549 #define CONFIG_PCI_PNP /* do pci plug-and-play */
552 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
553 #define CONFIG_DOS_PARTITION
554 #endif /* CONFIG_PCI */
557 #define CONFIG_FSL_SATA_V2
559 #ifdef CONFIG_FSL_SATA_V2
560 #define CONFIG_FSL_SATA
561 #define CONFIG_LIBATA
563 #define CONFIG_SYS_SATA_MAX_DEVICE 2
565 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
566 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
568 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
569 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
572 #define CONFIG_CMD_SATA
573 #define CONFIG_DOS_PARTITION
574 #define CONFIG_CMD_EXT2
577 #ifdef CONFIG_FMAN_ENET
578 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
579 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
580 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
581 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
582 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
584 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
585 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
586 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
587 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
589 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
591 #define CONFIG_SYS_TBIPA_VALUE 8
592 #define CONFIG_MII /* MII PHY management */
593 #define CONFIG_ETHPRIME "FM1@DTSEC1"
594 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
600 #define CONFIG_LOADS_ECHO /* echo on for serial download */
601 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
604 * Command line configuration.
606 #include <config_cmd_default.h>
608 #define CONFIG_CMD_DHCP
609 #define CONFIG_CMD_ELF
610 #define CONFIG_CMD_ERRATA
611 #define CONFIG_CMD_GREPENV
612 #define CONFIG_CMD_IRQ
613 #define CONFIG_CMD_I2C
614 #define CONFIG_CMD_MII
615 #define CONFIG_CMD_PING
616 #define CONFIG_CMD_SETEXPR
619 #define CONFIG_CMD_PCI
620 #define CONFIG_CMD_NET
626 #define CONFIG_HAS_FSL_DR_USB
627 #define CONFIG_HAS_FSL_MPH_USB
629 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
630 #define CONFIG_CMD_USB
631 #define CONFIG_USB_STORAGE
632 #define CONFIG_USB_EHCI
633 #define CONFIG_USB_EHCI_FSL
634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
637 #define CONFIG_CMD_EXT2
642 #define CONFIG_FSL_ESDHC
643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645 #define CONFIG_CMD_MMC
646 #define CONFIG_GENERIC_MMC
647 #define CONFIG_CMD_EXT2
648 #define CONFIG_CMD_FAT
649 #define CONFIG_DOS_PARTITION
653 * Miscellaneous configurable options
655 #define CONFIG_SYS_LONGHELP /* undef to save memory */
656 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
657 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
658 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
659 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
660 #ifdef CONFIG_CMD_KGDB
661 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
663 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
665 /* Print Buffer Size */
666 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
667 sizeof(CONFIG_SYS_PROMPT)+16)
668 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
669 /* Boot Argument Buffer Size */
670 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
671 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
674 * For booting Linux, the board info and command line data
675 * have to be in the first 64 MB of memory, since this is
676 * the maximum mapped by the Linux kernel during initialization.
678 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
679 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
681 #ifdef CONFIG_CMD_KGDB
682 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
683 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
687 * Environment Configuration
689 #define CONFIG_ROOTPATH "/opt/nfsroot"
690 #define CONFIG_BOOTFILE "uImage"
691 #define CONFIG_UBOOTPATH u-boot.bin
693 /* default location for tftp and bootm */
694 #define CONFIG_LOADADDR 1000000
696 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
698 #define CONFIG_BAUDRATE 115200
700 #define __USB_PHY_TYPE utmi
702 #define CONFIG_EXTRA_ENV_SETTINGS \
703 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
704 "bank_intlv=cs0_cs1\0" \
706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
708 "tftpflash=tftpboot $loadaddr $uboot && " \
709 "protect off $ubootaddr +$filesize && " \
710 "erase $ubootaddr +$filesize && " \
711 "cp.b $loadaddr $ubootaddr $filesize && " \
712 "protect on $ubootaddr +$filesize && " \
713 "cmp.b $loadaddr $ubootaddr $filesize\0" \
714 "consoledev=ttyS0\0" \
715 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
716 "usb_dr_mode=host\0" \
717 "ramdiskaddr=2000000\0" \
718 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
720 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
724 #define CONFIG_HDBOOT \
725 "setenv bootargs root=/dev/$bdev rw " \
726 "console=$consoledev,$baudrate $othbootargs;" \
727 "tftp $loadaddr $bootfile;" \
728 "tftp $fdtaddr $fdtfile;" \
729 "bootm $loadaddr - $fdtaddr"
731 #define CONFIG_NFSBOOTCOMMAND \
732 "setenv bootargs root=/dev/nfs rw " \
733 "nfsroot=$serverip:$rootpath " \
734 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
735 "console=$consoledev,$baudrate $othbootargs;" \
736 "tftp $loadaddr $bootfile;" \
737 "tftp $fdtaddr $fdtfile;" \
738 "bootm $loadaddr - $fdtaddr"
740 #define CONFIG_RAMBOOTCOMMAND \
741 "setenv bootargs root=/dev/ram rw " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "tftp $ramdiskaddr $ramdiskfile;" \
744 "tftp $loadaddr $bootfile;" \
745 "tftp $fdtaddr $fdtfile;" \
746 "bootm $loadaddr $ramdiskaddr $fdtaddr"
748 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
750 #ifdef CONFIG_SECURE_BOOT
751 #include <asm/fsl_secure_boot.h>
754 #endif /* __CONFIG_H */