2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 /* High Level Configuration Options */
30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
31 #define CONFIG_MP /* support multiple processors */
33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
38 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
39 #define CONFIG_PCIE1 /* PCIE controller 1 */
40 #define CONFIG_PCIE2 /* PCIE controller 2 */
41 #define CONFIG_PCIE3 /* PCIE controller 3 */
42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
43 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
45 #define CONFIG_SYS_SRIO
46 #define CONFIG_SRIO1 /* SRIO port 1 */
47 #define CONFIG_SRIO2 /* SRIO port 2 */
48 #define CONFIG_SRIO_PCIE_BOOT_MASTER
49 #define CONFIG_SYS_DPAA_RMAN /* RMan */
51 #define CONFIG_ENV_OVERWRITE
53 #ifndef CONFIG_MTD_NOR_FLASH
55 #define CONFIG_FLASH_CFI_DRIVER
56 #define CONFIG_SYS_FLASH_CFI
57 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
60 #if defined(CONFIG_SPIFLASH)
61 #define CONFIG_SYS_EXTRA_ENV_RELOC
62 #define CONFIG_ENV_SPI_BUS 0
63 #define CONFIG_ENV_SPI_CS 0
64 #define CONFIG_ENV_SPI_MAX_HZ 10000000
65 #define CONFIG_ENV_SPI_MODE 0
66 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
67 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
68 #define CONFIG_ENV_SECT_SIZE 0x10000
69 #elif defined(CONFIG_SDCARD)
70 #define CONFIG_SYS_EXTRA_ENV_RELOC
71 #define CONFIG_FSL_FIXED_MMC_LOCATION
72 #define CONFIG_SYS_MMC_ENV_DEV 0
73 #define CONFIG_ENV_SIZE 0x2000
74 #define CONFIG_ENV_OFFSET (512 * 1658)
75 #elif defined(CONFIG_NAND)
76 #define CONFIG_SYS_EXTRA_ENV_RELOC
77 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
78 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
79 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
80 #define CONFIG_ENV_ADDR 0xffe20000
81 #define CONFIG_ENV_SIZE 0x2000
82 #elif defined(CONFIG_ENV_IS_NOWHERE)
83 #define CONFIG_ENV_SIZE 0x2000
85 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
86 - CONFIG_ENV_SECT_SIZE)
87 #define CONFIG_ENV_SIZE 0x2000
88 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
92 unsigned long get_board_sys_clk(unsigned long dummy);
94 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
97 * These can be toggled for performance analysis, otherwise use default.
99 #define CONFIG_SYS_CACHE_STASHING
100 #define CONFIG_BACKSIDE_L2_CACHE
101 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
102 #define CONFIG_BTB /* toggle branch predition */
104 #define CONFIG_ENABLE_36BIT_PHYS
106 #ifdef CONFIG_PHYS_64BIT
107 #define CONFIG_ADDR_MAP
108 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
111 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
113 #define CONFIG_SYS_MEMTEST_END 0x00400000
114 #define CONFIG_SYS_ALT_MEMTEST
117 * Config the L3 Cache as L3 SRAM
119 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
120 #ifdef CONFIG_PHYS_64BIT
121 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
122 CONFIG_RAMBOOT_TEXT_BASE)
124 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
126 #define CONFIG_SYS_L3_SIZE (1024 << 10)
127 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_DCSRBAR 0xf0000000
131 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
135 #define CONFIG_ID_EEPROM
136 #define CONFIG_SYS_I2C_EEPROM_NXID
137 #define CONFIG_SYS_EEPROM_BUS_NUM 0
138 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
144 #define CONFIG_VERY_BIG_RAM
145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
149 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 #define CONFIG_DDR_SPD
153 #define CONFIG_SYS_SPD_BUS_NUM 0
154 #define SPD_EEPROM_ADDRESS 0x52
155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
158 * Local Bus Definitions
161 /* Set the local bus clock 1/8 of platform clock */
162 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
165 * This board doesn't have a promjet connector.
166 * However, it uses commone corenet board LAW and TLB.
167 * It is necessary to use the same start address with proper offset.
169 #define CONFIG_SYS_FLASH_BASE 0xe0000000
170 #ifdef CONFIG_PHYS_64BIT
171 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_FLASH_BR_PRELIM \
177 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
179 #define CONFIG_SYS_FLASH_OR_PRELIM \
180 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
181 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
183 #define CONFIG_FSL_CPLD
184 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
185 #ifdef CONFIG_PHYS_64BIT
186 #define CPLD_BASE_PHYS 0xfffdf0000ull
188 #define CPLD_BASE_PHYS CPLD_BASE
191 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
192 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
194 #define PIXIS_LBMAP_SWITCH 7
195 #define PIXIS_LBMAP_MASK 0xf0
196 #define PIXIS_LBMAP_SHIFT 4
197 #define PIXIS_LBMAP_ALTBANK 0x40
199 #define CONFIG_SYS_FLASH_QUIET_TEST
200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
209 #if defined(CONFIG_RAMBOOT_PBL)
210 #define CONFIG_SYS_RAMBOOT
213 #define CONFIG_NAND_FSL_ELBC
215 #ifdef CONFIG_NAND_FSL_ELBC
216 #define CONFIG_SYS_NAND_BASE 0xffa00000
217 #ifdef CONFIG_PHYS_64BIT
218 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
223 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
224 #define CONFIG_SYS_MAX_NAND_DEVICE 1
225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
227 /* NAND flash config */
228 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
229 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
230 | BR_PS_8 /* Port Size = 8 bit */ \
231 | BR_MS_FCM /* MSEL = FCM */ \
233 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
234 | OR_FCM_PGS /* Large Page*/ \
243 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
244 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
245 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
246 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
248 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
249 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
250 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
251 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
254 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
255 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
256 #endif /* CONFIG_NAND_FSL_ELBC */
258 #define CONFIG_SYS_FLASH_EMPTY_INFO
259 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
260 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
262 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
263 #define CONFIG_MISC_INIT_R
265 #define CONFIG_HWCONFIG
267 /* define to use L1 as initial stack */
268 #define CONFIG_L1_INIT_RAM
269 #define CONFIG_SYS_INIT_RAM_LOCK
270 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
271 #ifdef CONFIG_PHYS_64BIT
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
274 /* The assembler doesn't like typecast */
275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
283 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
285 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
286 GENERATED_GBL_DATA_SIZE)
287 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
289 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
290 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
292 /* Serial Port - controlled on board with jumper J8
296 #define CONFIG_CONS_INDEX 1
297 #define CONFIG_SYS_NS16550_SERIAL
298 #define CONFIG_SYS_NS16550_REG_SIZE 1
299 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
301 #define CONFIG_SYS_BAUDRATE_TABLE \
302 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
304 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
305 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
306 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
307 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
310 #define CONFIG_SYS_I2C
311 #define CONFIG_SYS_I2C_FSL
312 #define CONFIG_SYS_FSL_I2C_SPEED 400000
313 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
314 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
315 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
316 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
317 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
322 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
323 #ifdef CONFIG_PHYS_64BIT
324 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
326 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
328 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
330 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
334 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
336 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
339 * for slave u-boot IMAGE instored in master memory space,
340 * PHYS must be aligned based on the SIZE
342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
343 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
344 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
345 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
347 * for slave UCODE and ENV instored in master memory space,
348 * PHYS must be aligned based on the SIZE
350 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
351 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
352 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
354 /* slave core release by master*/
355 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
356 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
359 * SRIO_PCIE_BOOT - SLAVE
361 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
362 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
363 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
364 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
368 * eSPI - Enhanced SPI
370 #define CONFIG_SF_DEFAULT_SPEED 10000000
371 #define CONFIG_SF_DEFAULT_MODE 0
375 * Memory space is mapped 1-1, but I/O space must start from 0.
378 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
379 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
380 #ifdef CONFIG_PHYS_64BIT
381 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
382 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
384 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
385 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
387 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
388 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
389 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
390 #ifdef CONFIG_PHYS_64BIT
391 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
393 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
395 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
397 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
398 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
401 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
403 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
404 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
406 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
407 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
408 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
412 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
414 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
416 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
417 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
420 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
422 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
423 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
425 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
426 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
427 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
431 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
433 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
436 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
437 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
441 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
443 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
444 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
445 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
446 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
447 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
448 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
449 CONFIG_SYS_BMAN_CENA_SIZE)
450 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
451 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
452 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
453 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
457 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
459 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
460 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
461 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
462 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
463 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
464 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
465 CONFIG_SYS_QMAN_CENA_SIZE)
466 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
467 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
469 #define CONFIG_SYS_DPAA_FMAN
470 #define CONFIG_SYS_DPAA_PME
471 /* Default address of microcode for the Linux Fman driver */
472 #if defined(CONFIG_SPIFLASH)
474 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
475 * env, so we got 0x110000.
477 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
478 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
479 #elif defined(CONFIG_SDCARD)
481 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
482 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
483 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
485 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
486 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
487 #elif defined(CONFIG_NAND)
488 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
489 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
490 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
492 * Slave has no ucode locally, it can fetch this from remote. When implementing
493 * in two corenet boards, slave's ucode could be stored in master's memory
494 * space, the address can be mapped from slave TLB->slave LAW->
495 * slave SRIO or PCIE outbound window->master inbound window->
496 * master LAW->the ucode address in master's memory space.
498 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
499 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
501 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
502 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
504 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
505 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
507 #ifdef CONFIG_SYS_DPAA_FMAN
508 #define CONFIG_FMAN_ENET
509 #define CONFIG_PHYLIB_10G
510 #define CONFIG_PHY_VITESSE
511 #define CONFIG_PHY_TERANETICS
515 #define CONFIG_PCI_INDIRECT_BRIDGE
517 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
518 #endif /* CONFIG_PCI */
521 #define CONFIG_FSL_SATA_V2
523 #ifdef CONFIG_FSL_SATA_V2
524 #define CONFIG_SYS_SATA_MAX_DEVICE 2
526 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
527 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
529 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
530 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
535 #ifdef CONFIG_FMAN_ENET
536 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
537 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
538 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
539 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
540 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
542 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
543 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
544 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
545 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
547 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
549 #define CONFIG_SYS_TBIPA_VALUE 8
550 #define CONFIG_MII /* MII PHY management */
551 #define CONFIG_ETHPRIME "FM1@DTSEC1"
557 #define CONFIG_LOADS_ECHO /* echo on for serial download */
558 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
561 * Command line configuration.
567 #define CONFIG_HAS_FSL_DR_USB
568 #define CONFIG_HAS_FSL_MPH_USB
570 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
571 #define CONFIG_USB_EHCI_FSL
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
576 #define CONFIG_FSL_ESDHC
577 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
578 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
582 * Miscellaneous configurable options
584 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
587 * For booting Linux, the board info and command line data
588 * have to be in the first 64 MB of memory, since this is
589 * the maximum mapped by the Linux kernel during initialization.
591 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
592 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
594 #ifdef CONFIG_CMD_KGDB
595 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
599 * Environment Configuration
601 #define CONFIG_ROOTPATH "/opt/nfsroot"
602 #define CONFIG_BOOTFILE "uImage"
603 #define CONFIG_UBOOTPATH u-boot.bin
605 /* default location for tftp and bootm */
606 #define CONFIG_LOADADDR 1000000
608 #define __USB_PHY_TYPE utmi
610 #define CONFIG_EXTRA_ENV_SETTINGS \
611 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
612 "bank_intlv=cs0_cs1\0" \
614 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
615 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
616 "tftpflash=tftpboot $loadaddr $uboot && " \
617 "protect off $ubootaddr +$filesize && " \
618 "erase $ubootaddr +$filesize && " \
619 "cp.b $loadaddr $ubootaddr $filesize && " \
620 "protect on $ubootaddr +$filesize && " \
621 "cmp.b $loadaddr $ubootaddr $filesize\0" \
622 "consoledev=ttyS0\0" \
623 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
624 "usb_dr_mode=host\0" \
625 "ramdiskaddr=2000000\0" \
626 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
627 "fdtaddr=1e00000\0" \
628 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
631 #define CONFIG_HDBOOT \
632 "setenv bootargs root=/dev/$bdev rw " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr - $fdtaddr"
638 #define CONFIG_NFSBOOTCOMMAND \
639 "setenv bootargs root=/dev/nfs rw " \
640 "nfsroot=$serverip:$rootpath " \
641 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
642 "console=$consoledev,$baudrate $othbootargs;" \
643 "tftp $loadaddr $bootfile;" \
644 "tftp $fdtaddr $fdtfile;" \
645 "bootm $loadaddr - $fdtaddr"
647 #define CONFIG_RAMBOOTCOMMAND \
648 "setenv bootargs root=/dev/ram rw " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "tftp $ramdiskaddr $ramdiskfile;" \
651 "tftp $loadaddr $bootfile;" \
652 "tftp $fdtaddr $fdtfile;" \
653 "bootm $loadaddr $ramdiskaddr $fdtaddr"
655 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
657 #include <asm/fsl_secure_boot.h>
659 #endif /* __CONFIG_H */