3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 #include <galileo/core.h>
35 #include "../board/evb64260/local.h"
38 * High Level Configuration Options
42 #define CONFIG_P3G4 1 /* this is a P3G4 board */
43 #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
45 #define CONFIG_SYS_TEXT_BASE 0xfff00000
47 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
49 #undef CONFIG_ECC /* enable ECC support */
50 /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
52 /* which initialization functions to call for this board */
53 #define CONFIG_MISC_INIT_R 1
54 #define CONFIG_BOARD_EARLY_INIT_F 1
56 #define CONFIG_SYS_BOARD_NAME "P3G4"
58 #undef CONFIG_SYS_HUSH_PARSER
59 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
62 * The following defines let you select what serial you want to use
63 * for your console driver.
65 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
66 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
69 #define CONFIG_MPSC_PORT 0
71 #define CONFIG_NET_MULTI /* attempt all available adapters */
73 /* define this if you want to enable GT MAC filtering */
74 #define CONFIG_GT_USE_MAC_HASH_TABLE
76 #undef CONFIG_ETHER_PORT_MII /* use RMII */
79 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
81 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
83 #define CONFIG_ZERO_BOOTDELAY_CHECK
85 #define CONFIG_PREBOOT "echo;" \
86 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
89 #undef CONFIG_BOOTARGS
91 #define CONFIG_EXTRA_ENV_SETTINGS \
94 "nfsargs=setenv bootargs root=/dev/nfs rw " \
95 "nfsroot=${serverip}:${rootpath}\0" \
96 "ramargs=setenv bootargs root=/dev/ram rw\0" \
97 "addip=setenv bootargs ${bootargs} " \
98 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
99 ":${hostname}:${netdev}:off panic=1\0" \
100 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
101 "flash_nfs=run nfsargs addip addtty;" \
102 "bootm ${kernel_addr}\0" \
103 "flash_self=run ramargs addip addtty;" \
104 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
105 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
107 "rootpath=/opt/eldk/ppc_74xx\0" \
108 "bootfile=/tftpboot/p3g4/uImage\0" \
109 "kernel_addr=ff000000\0" \
110 "ramdisk_addr=ff010000\0" \
111 "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
112 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
113 "cp.b 100000 fff00000 ${filesize};" \
114 "setenv filesize;saveenv\0" \
115 "upd=run load update\0" \
117 #define CONFIG_BOOTCOMMAND "run flash_self"
119 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
120 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
122 #undef CONFIG_WATCHDOG /* watchdog disabled */
123 #undef CONFIG_ALTIVEC /* undef to disable */
128 #define CONFIG_BOOTP_SUBNETMASK
129 #define CONFIG_BOOTP_GATEWAY
130 #define CONFIG_BOOTP_HOSTNAME
131 #define CONFIG_BOOTP_BOOTPATH
132 #define CONFIG_BOOTP_BOOTFILESIZE
135 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
139 * Command line configuration.
141 #include <config_cmd_default.h>
143 #define CONFIG_CMD_ASKENV
144 #define CONFIG_CMD_DHCP
145 #define CONFIG_CMD_PCI
146 #define CONFIG_CMD_ELF
147 #define CONFIG_CMD_MII
148 #define CONFIG_CMD_PING
149 #define CONFIG_CMD_UNIVERSE
150 #define CONFIG_CMD_BSP
154 * Miscellaneous configurable options
156 #define CONFIG_SYS_LONGHELP /* undef to save memory */
157 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
158 #if defined(CONFIG_CMD_KGDB)
159 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
161 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
164 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
165 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
167 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
168 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
170 #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
172 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
173 #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
175 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
179 * Low Level Configuration Settings
180 * (address mappings, register initial values, etc.)
181 * You should know what you are doing if you make changes here.
184 /*-----------------------------------------------------------------------
185 * Definitions for initial stack pointer and data area
187 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
188 #define CONFIG_SYS_INIT_RAM_END 0x1000
189 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_RAM_LOCK
194 /*-----------------------------------------------------------------------
195 * Start addresses for the final memory configuration
196 * (Set up by the startup code)
197 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
199 #define CONFIG_SYS_SDRAM_BASE 0x00000000
200 #define CONFIG_SYS_FLASH_BASE 0xff000000
201 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
202 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
204 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
206 /* areas to map different things with the GT in physical space */
207 #define CONFIG_SYS_DRAM_BANKS 1
208 #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
210 /* What to put in the bats. */
211 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
213 /* Peripheral Device section */
214 #define CONFIG_SYS_GT_REGS 0xf8000000
215 #define CONFIG_SYS_DEV_BASE 0xff000000
217 #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
218 #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
219 #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
220 #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
222 #define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
223 #define CONFIG_SYS_DEV1_SIZE 0 /* unused */
224 #define CONFIG_SYS_DEV2_SIZE 0 /* unused */
225 #define CONFIG_SYS_DEV3_SIZE 0 /* unused */
227 #define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
228 #define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
230 #if 0 /* Wrong?? NTL */
231 #define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
232 /* DMAAck[1:0] GNT0[1:0] */
234 #define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
235 /* REQ0[1:0] GNT0[1:0] */
237 #define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
238 /* DMAReq[4] DMAAck[4] WDNMI WDE */
239 #if 0 /* Wrong?? NTL */
240 #define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
241 /* DMAAck[1:0] GNT1[1:0] */
243 #define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
244 /* GPP[22] (RS232IntB or PCI1Int) */
245 /* GPP[21] (RS323IntA) */
247 /* REQ1[1:0] GNT1[1:0] */
250 #if 0 /* Wrong?? NTL */
251 # define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
252 /* GPP[27:26] Int[1:0] */
254 # define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
255 /* GPP[29] (PCI1Int) */
257 /* GPP[27] (PCI0Int) */
258 /* GPP[26] (RtcInt or PCI1Int) */
262 #define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
264 #if 0 /* Wrong?? - NTL */
265 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
267 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
272 # define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
273 /* idmas use buffer 1,1
277 normal load (see also ifdef HVL)
278 standard SDRAM (see also ifdef REG)
279 non staggered refresh */
280 /* 31:26 25 23 20 19 18 16 */
281 /* 110110 00 111 0 0 00 1 */
282 /* refresh_count=0x200
283 phisical interleaving disable
284 virtual interleaving enable */
290 #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
291 #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
293 #undef CONFIG_SYS_INIT_CHAN1
294 #undef CONFIG_SYS_INIT_CHAN2
296 #define SRAM_BASE CONFIG_SYS_DEV0_SPACE
297 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
301 /*-----------------------------------------------------------------------
303 *-----------------------------------------------------------------------
306 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
307 #define PCI_HOST_FORCE 1 /* configure as pci host */
308 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
310 #define CONFIG_PCI /* include pci support */
311 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
312 #define CONFIG_PCI_PNP /* do pci plug-and-play */
314 /* PCI MEMORY MAP section */
315 #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
316 #define CONFIG_SYS_PCI0_MEM_SIZE _128M
317 #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
319 #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
320 #define CONFIG_SYS_PCI1_MEM_SIZE _128M
321 #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
323 /* PCI I/O MAP section */
324 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
325 #define CONFIG_SYS_PCI0_IO_SIZE _16M
326 #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
327 #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
329 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
330 #define CONFIG_SYS_PCI1_IO_SIZE _16M
331 #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
332 #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
334 /*----------------------------------------------------------------------
335 * Initial BAT mappings
339 * 1) GUARDED and WRITE_THRU not allowed in IBATS
340 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
344 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
345 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
346 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
347 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
350 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
351 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
352 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
353 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
355 /* PCI0, PCI1 in one BAT */
356 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
357 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
358 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
359 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
361 /* GT regs, bootrom, all the devices, PCI I/O */
362 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
363 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
364 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
365 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
367 /* I2C speed and slave address (for compatability) defaults */
368 #define CONFIG_SYS_I2C_SPEED 400000
369 #define CONFIG_SYS_I2C_SLAVE 0x7F
371 /* I2C addresses for the two DIMM SPD chips */
372 #ifndef CONFIG_EVB64260_750CX
373 #define DIMM0_I2C_ADDR 0x56
374 #define DIMM1_I2C_ADDR 0x54
375 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
376 #define DIMM0_I2C_ADDR 0x54
377 #define DIMM1_I2C_ADDR 0x54
381 * For booting Linux, the board info and command line data
382 * have to be in the first 8 MB of memory, since this is
383 * the maximum mapped by the Linux kernel during initialization.
385 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
387 /*-----------------------------------------------------------------------
390 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
391 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
393 #define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
394 #define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
395 #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
397 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
398 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
399 #define CONFIG_SYS_FLASH_CFI 1
401 #define CONFIG_ENV_IS_IN_FLASH 1
402 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
403 #define CONFIG_ENV_SECT_SIZE 0x20000
404 #define CONFIG_ENV_ADDR 0xFFFE0000
406 /*-----------------------------------------------------------------------
407 * Cache Configuration
409 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
410 #if defined(CONFIG_CMD_KGDB)
411 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
414 /*-----------------------------------------------------------------------
415 * L2CR setup -- make sure this is right for your board!
416 * look in include/74xx_7xx.h for the defines used here
419 #define CONFIG_SYS_L2
421 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
422 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
424 #define L2_ENABLE (L2_INIT | L2CR_L2E)
426 #define CONFIG_SYS_BOARD_ASM_INIT 1
429 #endif /* __CONFIG_H */