3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #include <asm/processor.h>
34 #include <galileo/core.h>
37 #include "../board/evb64260/local.h"
40 * High Level Configuration Options
44 #define CONFIG_P3G4 1 /* this is a P3G4 board */
45 #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
47 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
49 #undef CONFIG_ECC /* enable ECC support */
50 /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
52 /* which initialization functions to call for this board */
53 #define CONFIG_MISC_INIT_R 1
54 #define CONFIG_BOARD_PRE_INIT 1
56 #define CFG_BOARD_NAME "P3G4"
58 #undef CFG_HUSH_PARSER
59 #define CFG_PROMPT_HUSH_PS2 "> "
62 * The following defines let you select what serial you want to use
63 * for your console driver.
65 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
66 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
69 #define CONFIG_MPSC_PORT 1
71 #define CONFIG_NET_MULTI /* attempt all available adapters */
73 /* define this if you want to enable GT MAC filtering */
74 #define CONFIG_GT_USE_MAC_HASH_TABLE
76 #undef CONFIG_ETHER_PORT_MII /* use RMII */
79 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
81 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
83 #define CONFIG_ZERO_BOOTDELAY_CHECK
85 #undef CONFIG_BOOTARGS
86 #define CONFIG_BOOTCOMMAND \
88 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
89 "ip=$ipaddr:$serverip:$gatewayip:" \
90 "$netmask:$hostname:eth0:none; && " \
93 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
94 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
96 #undef CONFIG_WATCHDOG /* watchdog disabled */
97 #undef CONFIG_ALTIVEC /* undef to disable */
99 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
100 CONFIG_BOOTP_BOOTFILESIZE)
103 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV)
105 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106 #include <cmd_confdefs.h>
109 * Miscellaneous configurable options
111 #define CFG_LONGHELP /* undef to save memory */
112 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
113 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
114 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
116 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119 #define CFG_MAXARGS 16 /* max number of command args */
120 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
122 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
123 #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
125 #define CFG_LOAD_ADDR 0x00300000 /* default load address */
127 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
128 #define CFG_BUS_HZ 133000000 /* 133 MHz */
129 #define CFG_BUS_CLK CFG_BUS_HZ
131 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
135 * Low Level Configuration Settings
136 * (address mappings, register initial values, etc.)
137 * You should know what you are doing if you make changes here.
140 /*-----------------------------------------------------------------------
141 * Definitions for initial stack pointer and data area
143 #define CFG_INIT_RAM_ADDR 0x40000000
144 #define CFG_INIT_RAM_END 0x1000
145 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
146 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
147 #define CFG_INIT_RAM_LOCK
150 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration
152 * (Set up by the startup code)
153 * Please note that CFG_SDRAM_BASE _must_ start at 0
155 #define CFG_SDRAM_BASE 0x00000000
156 #define CFG_FLASH_BASE 0xff800000
157 #define CFG_RESET_ADDRESS 0xfff00100
158 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
159 #define CFG_MONITOR_BASE TEXT_BASE
160 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
162 /* areas to map different things with the GT in physical space */
163 #define CFG_DRAM_BANKS 1
164 #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
166 /* What to put in the bats. */
167 #define CFG_MISC_REGION_BASE 0xf0000000
169 /* Peripheral Device section */
170 #define CFG_GT_REGS 0xf8000000
171 #define CFG_DEV_BASE 0xff000000
173 #define CFG_DEV0_SPACE CFG_DEV_BASE
174 #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
175 #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
176 #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
178 #define CFG_DEV0_SIZE _8M /* Flash bank */
179 #define CFG_DEV1_SIZE 0 /* unused */
180 #define CFG_DEV2_SIZE 0 /* unused */
181 #define CFG_DEV3_SIZE 0 /* unused */
183 #define CFG_16BIT_BOOT_PAR 0xc01b5e7c
184 #define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR
186 #if 0 /* Wrong?? NTL */
187 #define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
188 /* DMAAck[1:0] GNT0[1:0] */
190 #define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
191 /* REQ0[1:0] GNT0[1:0] */
193 #define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
194 /* DMAReq[4] DMAAck[4] WDNMI WDE */
195 #if 0 /* Wrong?? NTL */
196 #define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
197 /* DMAAck[1:0] GNT1[1:0] */
199 #define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
200 /* GPP[22] (RS232IntB or PCI1Int) */
201 /* GPP[21] (RS323IntA) */
203 /* REQ1[1:0] GNT1[1:0] */
206 #if 0 /* Wrong?? NTL */
207 # define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
208 /* GPP[27:26] Int[1:0] */
210 # define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
211 /* GPP[29] (PCI1Int) */
213 /* GPP[27] (PCI0Int) */
214 /* GPP[26] (RtcInt or PCI1Int) */
218 #define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
220 #if 0 /* Wrong?? - NTL */
221 # define CFG_GPP_LEVEL_CONTROL 0x000002c6
223 # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
228 # define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
229 /* idmas use buffer 1,1
233 normal load (see also ifdef HVL)
234 standard SDRAM (see also ifdef REG)
235 non staggered refresh */
236 /* 31:26 25 23 20 19 18 16 */
237 /* 110110 00 111 0 0 00 1 */
238 /* refresh_count=0x200
239 phisical interleaving disable
240 virtual interleaving enable */
246 #define CFG_DUART_IO CFG_DEV2_SPACE
247 #define CFG_DUART_CHAN 1 /* channel to use for console */
249 #undef CFG_INIT_CHAN1
250 #undef CFG_INIT_CHAN2
252 #define SRAM_BASE CFG_DEV0_SPACE
253 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
257 /*-----------------------------------------------------------------------
259 *-----------------------------------------------------------------------
262 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
263 #define PCI_HOST_FORCE 1 /* configure as pci host */
264 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
266 #define CONFIG_PCI /* include pci support */
267 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
268 #define CONFIG_PCI_PNP /* do pci plug-and-play */
270 /* PCI MEMORY MAP section */
271 #define CFG_PCI0_MEM_BASE 0x80000000
272 #define CFG_PCI0_MEM_SIZE _128M
273 #define CFG_PCI1_MEM_BASE 0x88000000
274 #define CFG_PCI1_MEM_SIZE _128M
276 #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
277 #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
280 /* PCI I/O MAP section */
281 #define CFG_PCI0_IO_BASE 0xfa000000
282 #define CFG_PCI0_IO_SIZE _16M
283 #define CFG_PCI1_IO_BASE 0xfb000000
284 #define CFG_PCI1_IO_SIZE _16M
286 #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
287 #define CFG_PCI0_IO_SPACE_PCI 0x00000000
288 #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
289 #define CFG_PCI1_IO_SPACE_PCI 0x00000000
291 /*----------------------------------------------------------------------
292 * Initial BAT mappings
296 * 1) GUARDED and WRITE_THRU not allowed in IBATS
297 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
301 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
302 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
303 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
304 #define CFG_DBAT0U CFG_IBAT0U
307 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
308 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
309 #define CFG_DBAT1L CFG_IBAT1L
310 #define CFG_DBAT1U CFG_IBAT1U
312 /* PCI0, PCI1 in one BAT */
313 #define CFG_IBAT2L BATL_NO_ACCESS
314 #define CFG_IBAT2U CFG_DBAT2U
315 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
316 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
318 /* GT regs, bootrom, all the devices, PCI I/O */
319 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
320 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
321 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
322 #define CFG_DBAT3U CFG_IBAT3U
324 /* I2C speed and slave address (for compatability) defaults */
325 #define CFG_I2C_SPEED 400000
326 #define CFG_I2C_SLAVE 0x7F
328 /* I2C addresses for the two DIMM SPD chips */
329 #ifndef CONFIG_EVB64260_750CX
330 #define DIMM0_I2C_ADDR 0x56
331 #define DIMM1_I2C_ADDR 0x54
332 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
333 #define DIMM0_I2C_ADDR 0x54
334 #define DIMM1_I2C_ADDR 0x54
338 * For booting Linux, the board info and command line data
339 * have to be in the first 8 MB of memory, since this is
340 * the maximum mapped by the Linux kernel during initialization.
342 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
344 /*-----------------------------------------------------------------------
347 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
348 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
350 #define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */
351 #define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */
352 #define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
354 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
355 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
356 #define CFG_FLASH_CFI 1
358 #define CFG_ENV_IS_IN_FLASH 1
359 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
360 #define CFG_ENV_SECT_SIZE 0x20000
361 #define CFG_ENV_ADDR 0xFFFE0000
363 /*-----------------------------------------------------------------------
364 * Cache Configuration
366 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
367 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
368 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
371 /*-----------------------------------------------------------------------
372 * L2CR setup -- make sure this is right for your board!
373 * look in include/74xx_7xx.h for the defines used here
378 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
379 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
381 #define L2_ENABLE (L2_INIT | L2CR_L2E)
384 * Internal Definitions
388 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
389 #define BOOTFLAG_WARM 0x02 /* Software reboot */
391 #define CFG_BOARD_ASM_INIT 1
394 #endif /* __CONFIG_H */