2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
16 #define CONFIG_MPC5200
17 #define CONFIG_PM520 1 /* PM520 board */
19 #define CONFIG_SYS_TEXT_BASE 0xfff00000
21 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
23 #define CONFIG_MISC_INIT_R
25 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
28 * Serial console configuration
30 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
31 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
32 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
37 * 0x40000000 - 0x4fffffff - PCI Memory
38 * 0x50000000 - 0x50ffffff - PCI IO Space
41 #define CONFIG_PCI_PNP 1
42 #define CONFIG_PCI_SCAN_SHOW 1
43 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
45 #define CONFIG_PCI_MEM_BUS 0x40000000
46 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
47 #define CONFIG_PCI_MEM_SIZE 0x10000000
49 #define CONFIG_PCI_IO_BUS 0x50000000
50 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
51 #define CONFIG_PCI_IO_SIZE 0x01000000
54 #define CONFIG_EEPRO100 1
55 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
60 #define CONFIG_DOS_PARTITION
64 #define CONFIG_USB_OHCI
65 #define CONFIG_USB_STORAGE
71 #define CONFIG_BOOTP_BOOTFILESIZE
72 #define CONFIG_BOOTP_BOOTPATH
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
78 * Command line configuration.
80 #include <config_cmd_default.h>
82 #define CONFIG_CMD_BEDBUG
83 #define CONFIG_CMD_DATE
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_EEPROM
86 #define CONFIG_CMD_FAT
87 #define CONFIG_CMD_I2C
88 #define CONFIG_CMD_IDE
89 #define CONFIG_CMD_NFS
90 #define CONFIG_CMD_SNTP
91 #define CONFIG_CMD_USB
93 #define CONFIG_CMD_PCI
99 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
101 #define CONFIG_PREBOOT "echo;" \
102 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
105 #undef CONFIG_BOOTARGS
107 #define CONFIG_EXTRA_ENV_SETTINGS \
110 "nfsargs=setenv bootargs root=/dev/nfs rw " \
111 "nfsroot=${serverip}:${rootpath}\0" \
112 "ramargs=setenv bootargs root=/dev/ram rw\0" \
113 "addip=setenv bootargs ${bootargs} " \
114 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
115 ":${hostname}:${netdev}:off panic=1\0" \
116 "flash_nfs=run nfsargs addip;" \
117 "bootm ${kernel_addr}\0" \
118 "flash_self=run ramargs addip;" \
119 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
120 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
121 "rootpath=/opt/eldk30/ppc_82xx\0" \
122 "bootfile=/tftpboot/PM520/uImage\0" \
125 #define CONFIG_BOOTCOMMAND "run flash_self"
128 * IPB Bus clocking configuration.
130 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
134 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
135 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
137 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
138 #define CONFIG_SYS_I2C_SLAVE 0x7F
141 * EEPROM configuration
143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
151 #define CONFIG_RTC_PCF8563
152 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
154 #define CONFIG_SYS_DOC_BASE 0xE0000000
155 #define CONFIG_SYS_DOC_SIZE 0x00100000
157 #if defined(CONFIG_BOOT_ROM)
159 * Flash configuration (8,16 or 32 MB)
160 * TEXT base always at 0xFFF00000
161 * ENV_ADDR always at 0xFFF40000
162 * FLASH_BASE at 0xFA000000 for 64 MB
163 * 0xFC000000 for 32 MB
164 * 0xFD000000 for 16 MB
165 * 0xFD800000 for 8 MB
167 #define CONFIG_SYS_FLASH_BASE 0xFA000000
168 #define CONFIG_SYS_FLASH_SIZE 0x04000000
169 #define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
170 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
171 #define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
174 * Flash configuration (8,16 or 32 MB)
175 * TEXT base always at 0xFFF00000
176 * ENV_ADDR always at 0xFFF40000
177 * FLASH_BASE at 0xFC000000 for 64 MB
178 * 0xFE000000 for 32 MB
179 * 0xFF000000 for 16 MB
180 * 0xFF800000 for 8 MB
182 #define CONFIG_SYS_FLASH_BASE 0xFC000000
183 #define CONFIG_SYS_FLASH_SIZE 0x04000000
184 #define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
190 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
192 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
193 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
194 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
196 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
198 #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
202 * Environment settings
204 #define CONFIG_ENV_IS_IN_FLASH 1
205 #define CONFIG_ENV_SIZE 0x10000
206 #define CONFIG_ENV_SECT_SIZE 0x40000
207 #define CONFIG_ENV_OVERWRITE 1
212 #define CONFIG_SYS_MBAR 0xf0000000
213 #define CONFIG_SYS_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
216 /* Use SRAM until RAM will be available */
217 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
218 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
221 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
226 # define CONFIG_SYS_RAMBOOT 1
229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
230 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
231 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
234 * Ethernet configuration
236 #define CONFIG_MPC5xxx_FEC 1
237 #define CONFIG_MPC5xxx_FEC_MII100
239 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
241 /* #define CONFIG_MPC5xxx_FEC_MII10 */
242 #define CONFIG_PHY_ADDR 0x00
247 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
250 * Miscellaneous configurable options
252 #define CONFIG_SYS_LONGHELP /* undef to save memory */
253 #if defined(CONFIG_CMD_KGDB)
254 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
256 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
259 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
260 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
262 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
263 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
265 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
267 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
268 #if defined(CONFIG_CMD_KGDB)
269 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
273 * Various low-level settings
275 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
276 #define CONFIG_SYS_HID0_FINAL HID0_ICE
278 #if defined(CONFIG_BOOT_ROM)
279 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
280 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
281 #define CONFIG_SYS_BOOTCS_CFG 0x00047800
282 #define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
283 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
284 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
285 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
286 #define CONFIG_SYS_CS1_CFG 0x0004FF00
288 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
289 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
290 #define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
291 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
292 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
293 #define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
294 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
295 #define CONFIG_SYS_CS1_CFG 0x00047800
298 #define CONFIG_SYS_CS_BURST 0x00000000
299 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
301 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
303 /*-----------------------------------------------------------------------
305 *-----------------------------------------------------------------------
307 #define CONFIG_USB_CLOCK 0x0001BBBB
308 #define CONFIG_USB_CONFIG 0x00005000
310 /*-----------------------------------------------------------------------
311 * IDE/ATA stuff Supports IDE harddisk
312 *-----------------------------------------------------------------------
315 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
317 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
318 #undef CONFIG_IDE_LED /* LED for ide not supported */
320 #undef CONFIG_IDE_RESET /* reset for ide supported */
321 #define CONFIG_IDE_PREINIT
323 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
324 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
326 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
328 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
330 /* Offset for data I/O */
331 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
333 /* Offset for normal register accesses */
334 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
336 /* Offset for alternate registers */
337 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
339 /* Interval between registers */
340 #define CONFIG_SYS_ATA_STRIDE 4
342 #endif /* __CONFIG_H */